- 2.13.2. Clock-to-Data Ratio for Bitstream Encryption and Compression ( Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs)
2.7.8. Promoting Global Signals in a PR Region
In PR designs, the Compiler disables global promotion for signals originating within the logic of a PR region. Instantiate the clock control blocks only in the static region, because the clock floorplan and the clock buffers must be a part of the static region of the design. Manually instantiating a clock control block in a PR region, or assigning a signal in a PR region with the GLOBAL_SIGNAL assignment, results in compilation error. To drive a signal originating from the PR region onto a global network:
- Expose the signal from the PR region.
- Drive the signal onto the global network from the static region.
- Drive the signal back into the PR region.
You can drive a maximum of 33 clocks (for Intel® Arria® 10 and Intel® Cyclone® 10 GX devices), or 32 clocks (for Intel® Agilex™ and Intel® Stratix® 10 devices) into any PR region. You cannot share a row clock between two PR regions.
The Compiler allows only certain signals to be global inside a PR region. Use only global signals to route secondary signals into a PR region, as the following table describes:
|Block Type||Supported Global Network Signals|
|LAB, MLAB||Clock, ACLR, SCLR4|
|RAM, ROM (M20K)||Clock, ACLR, Write Enable (WE), Read Enable (RE), SCLR|
|DSP||Clock, ACLR, SCLR|
Viewing Row Clock Region Boundaries
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