3.3.1. Agent Interface
The Partial Reconfiguration Controller Intel® Arria® 10 /Cyclone 10 FPGA IP provides an Avalon® memory-mapped agent interface to read and write to PR configuration registers.
Every data write to this address indicates this bitstream is sent to the IP core.
Performing a read on this address returns all 0's.
|PR_CSR||0x01||Read or Write||Control and status registers.|
Read-only SW version register. Register is currently 0xAA500003
|PR Bitstream ID||0x03||Read-Only||Read-only PR POF ID register|
Read and write control register for pr_start signal. Refer to Ports for details on the pr_start signal.
pr_start = PR_CSR
The IP core deasserts PR_CSR to value 0 automatically, one clock cycle after the PR_CSR asserts. This streamlines the flow to avoid manual assertion and de-assertion of this register to control pr_start signal.
Read-only status register for status[2:0] signal.
PR_CSR[4:2] = status[2:0]
Refer to Ports for details on the status signals.
Read and clear bit for interrupt.
If you enable the interrupt interface, reading this bit returns the value of the irq signal. Writing a 1 clears the interrupt.
If you disable the interrupt interface, reading this bit always returns a value of 0.
|6-31||Reserved bits. Depends on the Avalon® memory-mapped data bus width.|
Did you find the information on this page useful?