- 2.13.2. Clock-to-Data Ratio for Bitstream Encryption and Compression ( Intel® Arria® 10 or Intel® Cyclone® 10 GX Designs)
2.6. Partial Reconfiguration Design Flow
The PR design flow requires initial planning. This planning involves setting up one or more design partitions, and then determining the placement assignments in the floorplan. Well-planned PR partitions improve design area utilization and performance. The Intel® Quartus® Prime software also allows you to create nested PR regions as part of an HPR flow.
The PR design flow uses the project revisions feature in the Intel® Quartus® Prime software. Your initial design is the base revision, where you define the static region boundaries and reconfigurable regions on the FPGA. From the base revision, you create multiple revisions. These revisions contain the different implementations for the PR regions. However, all PR implementation revisions use the same top-level placement and routing results from the base revision.
The PR design flow includes the following steps:
- Step 1: Identify Partial Reconfiguration Resources
- Step 2: Create Design Partitions
- Step 3: Floorplan the Design
- Step 4: Add the Partial Reconfiguration Controller Intel FPGA IP
- Step 5: Define Personas
- Step 6: Create Revisions for Personas
- Step 7: Compile the Base Revision and Export the Static Region
- Step 8: Setup PR Implementation Revisions
- Step 9: Program the FPGA Device
Step 1: Identify Partial Reconfiguration Resources
Step 2: Create Design Partitions
Step 3: Floorplan the Design
Step 4: Add the Partial Reconfiguration Controller Intel FPGA IP
Step 5: Define Personas
Step 6: Create Revisions for Personas
Step 7: Compile the Base Revision and Export the Static Region
Step 8: Setup PR Implementation Revisions
Step 9: Program the FPGA Device
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