3.2.1. Memory Map
Every data write to this address indicates this bitstream is sending to the IP core.
Width is set by the Input data width parameter.
|PR_CSR||0x01||32||Read or Write||Control and status registers with the following offset bits:
|PR_SW_VER||0x02||32||Read||Read-only SW version register. Register is currently 0xBA500000.|
|PR_FW_HANDSHAKE||0x03||32||Read||Current location of mailbox handshake between the PR IP and the SDM in the PR operation with the following offset bits:
|PR_FW_RESPONSE||0x04||32||Read||SDM mailbox response. You must use this in conjunction with PR_FW_HANDSHAKE. If PR_FW_HANDSHAKE is 0x2 or 0x6, the following offset bits apply:
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