Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 10/06/2023
Public

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6.1. Top-Level Settings

Figure 27. Multi Channel DMA IP for PCI Express Parameter Editor
Table 70.  Top-Level Settings

Parameter

Value

Default Value

Description

Hard IP mode (P-Tile)

Gen4 x16, Interface – 512 bit

Gen3 x16, Interface – 512 bit

Gen4 2x8, Interface - 256 bit

Gen3 2x8, Interface - 256 bit

Gen4 1x8, Interface – 256 bit

Gen3 1x8, Interface – 256 bit

Gen4 4x4, Interface - 128 bit

Gen3 4x4, Interface - 128 bit

Gen4x16, Interface – 512 bit

Selects the following elements:
  • Lane data rate: Gen3 and Gen4 are supported.
  • Lane width: x16 supports both Root Port and Endpoint modes. 1 x8, 2 x8 support only Endpoint mode. 4 x4 mode only supports Root Port mode.
Hard IP mode (F-Tile)

Gen4 x16, Interface – 512 bit

Gen3 x16, Interface – 512 bit

Gen4 2x8, Interface - 256 bit

Gen3 2x8, Interface - 256 bit

Gen4 1x8, Interface – 256 bit

Gen3 1x8, Interface – 256 bit

Gen4 1x4, Interface - 128 bit

Gen3 1x4, Interface - 128 bit

Gen4 2x4, Interface - 128 bit

Gen3 2x4, Interface - 128 bit

Gen4 4x4, Interface - 128 bit

Gen3 4x4, Interface - 128 bit

Gen4x16, Interface – 512 bit

Selects the following elements:
  • Lane data rate: Gen3 and Gen4 are supported.
  • Lane width: x16 and 1 x8 support both Root Port and Endpoint mode. 2 x8 and 1 x4 support only Endpoint mode. 2 x4 and 4 x4 support only Root Port mode.
Hard IP mode (R-Tile)

Gen4 x16, Interface – 512 bit

Gen3 x16, Interface – 512 bit

Gen5 2x8, Interface – 512 bit

Gen4 2x8, Interface - 512 bit

Gen3 2x8, Interface - 512 bit

Gen4 2x8, Interface – 256 bit

Gen3 2x8, Interface – 256 bit

Gen5 4x4, Interface - 256 bit

Gen4 4x4, Interface - 256 bit

Gen3 4x4, Interface - 256 bit

Gen4 4x4, Interface - 128 bit

Gen3 4x4, Interface - 128 bit

Gen5 2x8, Interface – 512 bit
Selects the following elements:
  • Link data rate: Gen5, Gen4 and Gen3 are supported.
  • Link width: x16, x8 and x4 modes supported for both Root Port and Endpoint
DK-DEV-AGI0227RES R-Tile A0 revision only supports:
  • Gen5 2x8, Interface - 512 bit
  • Gen4 2x8, Interface - 512 bit
  • Gen3 2x8, Interface - 512 bit
Number of PCIe 1 / 2 1

Display total number of MCDMA IP cores in x8 mode.

Port Mode

Native Endpoint

Root Port

Native Endpoint

Specifies the port type.

Root Port mode: x16,1x8 (F-Tile only), 2x8 (R-Tile only), 2x4 (F-Tile only), 4x4

Endpoint mode: x16, 1x8, 2x8, 1x4 (F-Tile only), 4x4 (R-Tile only)

Note: 1x8 is not supported for R-Tile
Note: In R-Tile 4x4, Port mode has several options EP/EP/EP/EP or EP/EP/RP/RP or EP/RP/RP/RP or RP/RP/RP/RP.

Enable Ptile Debug Toolkit (P-Tile)

Enable Debug Toolkit (F-Tile and R-Tile)

On / Off

Off

Enable the Debug Toolkit for JTAG-based System Console debug access.

Enable PHY Reconfiguration

On / Off

Off

When on, creates an Avalon-MM slave interface that software can drive to update Transceiver reconfiguration registers

Enable the transceiver PMA registers access through a dedicated an Avalon-MM slave interface.

Note: In F-Tile, this option has renamed as Enable PMA registers access
Note: This parameter is not supported for R-Tile

PLD Clock Frequency (P-Tile and F-Tile)

500 MHz

450 MHz

400 MHz

350 MHz

250 MHz

225 MHz

200 MHz

175 MHz

350 MHz (for Gen4 modes)

250 MHz (for Gen3 modes)

Select the frequency of the Application clock. The options available vary depending on the setting of the Hard IP Mode parameter.

For Gen4 modes, the available clock frequencies are 500 MHz / 450 MHz / 400 MHz / 350 MHz / 250 MHz / 225 MHz / 200 MHz / 175 MHz (for Intel Agilex® 7) and 400 MHz / 350 MHz / 200 MHz /175 MHz (for Intel Stratix 10 DX).

For Gen3 modes, the available clock frequency is 250 MHz (for Intel Agilex® 7 and Intel Stratix 10 DX).

PLD Clock Frequency (R-Tile)

500 MHz

475 MHz

450 MHz

425 MHz

400 MHz

350 MHz

275 MHz

250 MHz

500 MHz (for Gen5 mode)

500 MHz or 300 MHz (for Gen4 mode)

250 MHz (for Gen3 mode)

Selects the frequency of the Application clock. The options available vary depending on the setting of the Hard IP Mode parameter.

For Gen5 modes, the available clock frequencies are 500 MHz / 475 MHz / 450 MHz / 425 MHz / 400 MHz

For Gen4 modes, the available clock frequencies are 500 MHz / 475 MHz / 450 MHz / 425 MHz / 400 MHz / 300 MHz / 275 MHz / 250 MHz

For Gen3 modes, the available clock frequency are 300 MHz / 275 MHz / 250 MHz

Enable SRIS Mode

On / Off

Off

Enable the Separate Reference Clock with Independent Spread Spectrum Clocking (SRIS) feature.

When you enable this option, the Slot clock configuration option under the PCIe Settings → PCIe PCI Express/PCI Capabilities → PCIe Link tab will be automatically disabled.

P-Tile Sim Mode

On / Off

Off

Enabling this parameter reduces the simulation time of Hot Reset tests by 5 ms.

Note: Do not enable this option if you need to run synthesis.
Note: This parameter is not supported for R-Tile and F-Tile.

Enable PIPE Mode Simulation

On / Off

Off

When you set this parameter, the PIPE interface is exposed which can be used to improve the simulation time.

Note: This parameter is only supported for R-Tile MCDMA IP.
Note: This parameter is present in F-Tile MCDMA IP. However, F-Tile MCDMA Design Examples do not support PIPE mode Simulation.
Note: When running simulations with the PIPE interface, the following macro is required: "+define+RTILE_PIPE_MODE"

For more information regarding PIPE Mode Simulation feature and its usage, refer to R-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide.

Enable Independent Perst (P-Tile and F-Tile)

Enable Independent GPIO Perst (R-Tile)

On / Off Off

Enable the reset of PCS and Controller in User Mode for Endpoint 2x8 mode.

When this parameter is On, new signals p<n>_cold_perst_n_i and p<n>_warm_perst_n_i are exported to the user application for P/R-Tiles. In case of F-Tile, i_gpio_perst#_n is exported to the user application..

When this parameter is Off (default), the IP internally ties off these signals instead of exporting them.

Note: This parameter is required for the independent reset feature, which is only supported in the x8x8 Endpoint/Endpoint mode. In F-Tile, the Hard IP Reconfiguration Interface must be enabled and p0_hip_reconfig_clk port must be connected to a clock source when it is using this reset signal or Enable Independent Perst option is turned on.
Enable CVP (Intel VSEC) On / Off Off

Enable support for CVP flow for single tile only

Refer to Intel Agilex® 7 Device Configuration via Protocol (CvP) Implementation User Guide for more information

Slow Clock Divider

2 & 4

4

Allows you to set the slow_clk to be divided by 2 or 4 from the coreclkout_hip.

Note: This parameter is supported for R-Tile only.