Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 10/06/2023
Public

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3. Functional Description

Figure 2. Multi Channel DMA IP for PCI Express Block Diagram

Not all the blocks co-exist in a design. Required functional blocks are enabled based on the user mode that you select when you configure the IP. The following table shows valid user modes that Multi Channel DMA IP for PCI Express supports. Each row indicates a user mode with required block(s).

Table 16.  Valid user modes and required functional blocks
Mode MCDMA Bursting Master (BAM) Bursting Slave (BAS) Config Slave (CS) Data Mover
Endpoint MCDMA × × × ×
BAM × × × ×
BAS × × × ×
BAM+BAS × × ×
BAM+MCDMA × × ×
BAM+BAS+MCDMA × ×
Data Mover Only × × ×
Root Port BAM × × ×
BAS × × ×
BAM+BAS × ×
Note: Data mover only mode is not available for x4 topology in P/F/R-Tile MCDMA IPs.