Visible to Intel only — GUID: nxx1589414264355
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1. Before You Begin
2. Introduction
3. Functional Description
4. Interface Overview
5. Parameters (H-Tile)
6. Parameters (P-Tile) (F-Tile) (R-Tile)
7. Designing with the IP Core
8. Software Programming Model
9. Registers
10. Troubleshooting/Debugging
11. Multi Channel DMA Intel FPGA IP for PCI Express User Guide Archives
12. Revision History for the Multi Channel DMA Intel FPGA IP for PCI Express User Guide
3.1. Multi Channel DMA
3.2. Bursting Avalon-MM Master (BAM)
3.3. Bursting Avalon-MM Slave (BAS)
3.4. MSI Interrupt
3.5. Config Slave (CS)
3.6. Root Port Address Translation Table Enablement
3.7. Hard IP Reconfiguration Interface
3.8. Config TL Interface
3.9. Configuration Intercept Interface (EP Only)
3.10. Data Mover Only
4.1. Port List
4.2. Clocks
4.3. Resets
4.4. Multi Channel DMA
4.5. Bursting Avalon-MM Master (BAM) Interface
4.6. Bursting Avalon-MM Slave (BAS) Interface
4.7. MSI Interface
4.8. Config Slave Interface (RP only)
4.9. Hard IP Reconfiguration Interface
4.10. Config TL Interface
4.11. Configuration Intercept Interface (EP Only)
4.12. Data Mover Interface
4.13. Hard IP Status Interface
8.1.6.1. ifc_api_start
8.1.6.2. ifc_mcdma_port_by_name
8.1.6.3. ifc_qdma_device_get
8.1.6.4. ifc_num_channels_get
8.1.6.5. ifc_qdma_channel_get
8.1.6.6. ifc_qdma_acquire_channels
8.1.6.7. ifc_qdma_release_all_channels
8.1.6.8. ifc_qdma_device_put
8.1.6.9. ifc_qdma_channel_put
8.1.6.10. ifc_qdma_completion_poll
8.1.6.11. ifc_qdma_request_start
8.1.6.12. ifc_qdma_request_prepare
8.1.6.13. ifc_qdma_descq_queue_batch_load
8.1.6.14. ifc_qdma_request_submit
8.1.6.15. ifc_qdma_pio_read32
8.1.6.16. ifc_qdma_pio_write32
8.1.6.17. ifc_qdma_pio_read64
8.1.6.18. ifc_qdma_pio_write64
8.1.6.19. ifc_qdma_pio_read128
8.1.6.20. ifc_qdma_pio_write128
8.1.6.21. ifc_qdma_pio_read256
8.1.6.22. ifc_qdma_pio_write256
8.1.6.23. ifc_request_malloc
8.1.6.24. ifc_request_free
8.1.6.25. ifc_app_stop
8.1.6.26. ifc_qdma_poll_init
8.1.6.27. ifc_qdma_poll_add
8.1.6.28. ifc_qdma_poll_wait
8.1.6.29. ifc_mcdma_port_by_name
Visible to Intel only — GUID: nxx1589414264355
Ixiasoft
9. Registers
The Multi Channel DMA IP for PCI Express provides configuration, control and status registers to support the DMA operations including:
- D2H and H2D Queue control and status (QCSR)
- MSI-X Table and PBA for interrupt generation
- General/global DMA control (GCSR)
Note: GCSR is only for PF0.
Note: Read/Write access to CSR address space is limited to 32-bits at a time through the Mrd / Mwr commands from the host.
Following table shows 4 MB aperture space mapped for PF0 in PCIe config space through BAR0.
Address Space Name | Range | Size | Description |
---|---|---|---|
QCSR (D2H, H2D) | 22’h00_0000 - 22’h0F_FFFF | 1MB | Individual queue control registers. Up to 2048 D2H and 2048 H2D queues. |
MSI-X (Table and PBA) | 22’h10_0000 - 22’h1F_FFFF | 1MB | MSI-X Table and PBA space |
GCSR | 22’h20_0000 - 22’h2F_FFFF | 1MB | General DMA control and status registers. |
Reserved | 22’h30_0000 – 22’h3F_FFFF | 1MB | Reserved |
Following table shows how QCSR registers for each DMA channel are mapped with 1 MB space of QCSR.
Address Space Name | Size | DMA Channel | Size | Description |
---|---|---|---|---|
QCSR (D2H) | 512 KB | DMA Channel 0 | 256 B | QCSR for DMA channel 0 |
DMA Channel 1 | 256 B | QCSR for DMA channel 1 | ||
…. | …. | …. | ||
DMA Channel N | 256 B | QCSR for DMA channel N | ||
QCSR (H2D) | 512 KB | DMA Channel 0 | 256 B | QCSR for DMA channel 0 |
DMA Channel 1 | 256 B | QCSR for DMA channel 1 | ||
…. | …. | …. | ||
DMA Channel N | 256 B | QCSR for DMA channel 2 |