Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 10/06/2023
Public

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10.1.4.1. Main View

The main view tab lists a summary of the transmitter and receiver settings per channel for the given instance of the PCIe IP.

The following table shows the channel mapping when using subdivided ports.

Table 161.  Channel Mapping for Subdivided Ports
Toolkit Channel x16 Mode x8 Mode x4 Mode 2x8 Mode
Lane 0 Lane 0 Lane 0 Lane 0 Lane 0
Lane 1 Lane 1 Lane 1 Lane 1 Lane 1
Lane 2 Lane 2 Lane 2 Lane 2 Lane 2
Lane 3 Lane 3 Lane 3 Lane 3 Lane 3
Lane 4 Lane 4 Lane 4 N/A Lane 4
Lane 5 Lane 5 Lane 5 N/A Lane 5
Lane 6 Lane 6 Lane 6 N/A Lane 6
Lane 7 Lane 7 Lane 7 N/A Lane 7
Lane 8 Lane 8 N/A N/A Lane 0
Lane 9 Lane 9 N/A N/A Lane 1
Lane 10 Lane 10 N/A N/A Lane 2
Lane 11 Lane 11 N/A N/A Lane 3
Lane 12 Lane 12 N/A N/A Lane 4
Lane 13 Lane 13 N/A N/A Lane 5
Lane 14 Lane 14 N/A N/A Lane 6
Lane 15 Lane 15 N/A N/A Lane 7