Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 10/06/2023
Public

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6.2.4.3. PCIe0 MSI-X

Note: The PCIe0 MSI-X feature parameters cannot be set or modified if you select the MCDMA mode.
Note: The PCIe0 MSI-X feature parameters can be modified on BAS/BAM/BAM+BAS mode.
Table 77.  PCIe0 PF MSI-X
Parameter Value Description

Enable MSI-X

On / Off

When On, adds the MSI-X capability structure, with the parameters shown below.

Table size

15

System software reads this field to determine the MSI-X table size <n>, which is encoded as <n-1>.

Table offset

0x0000000000020000

Points to the base of the MSI-X table. The lower 3 bits of the table BAR indicator (BIR) are set to zero by software to form a 64-bit qword-aligned offset. This field is read-only after being programmed.

Table BAR indicator

0

Specifies which one of a function's base address registers, located beginning at 0x10 in the Configuration Space, maps the MSI-X table into memory space. This field is read-only.

Pending bit array (PBA) offset

0x0000000000030000

Used as an offset from the address contained in one of the function's Base Address registers to point to the base of the MSI-X PBA. The lower 3 bits of the PBA BIR are set to zero by software to form a 32-bit qword-aligned offset. This field is read-only after being programmed

PBA BAR indicator

0

Specifies the function Base Address registers, located beginning at 0x10 in Configuration Space, that maps the MSI-X PBA into memory space. This field is read-only in the MSI-X Capability Structure.

VF Table size

0

Sets the number of entries in the MSI-X table for PF0's VFs.

MSI-X cannot be disabled for VF. Set to 1 to save resources.

Table 78.  PCIe0 VF MSI-X
Parameter Value Description
Enable VF MSI-X On / Off

When On, adds the MSI-X capability structure to the VF, with the parameters shown below.

Table size 15

System software reads this field to determine the VF MSI-X table size <n>, which is encoded as <n-1>.

Table offset 0x0000000000020000

Points to the base of the VF MSI-X table. The lower 3 bits of the table BAR indicator (BIR) are set to zero by software to form a 64-bit qword-aligned offset. This field is read-only after being programmed.

Table BAR indicator 0

Specifies which one of a function's base address registers, located beginning at 0x10 in the Configuration Space, maps the VF MSI-X table into memory space. This field is read-only.

Pending bit array (PBA) offset 0x0000000000030000

Used as an offset from the address contained in one of the function's Base Address registers to point to the base of the VF MSI-X PBA. The lower 3 bits of the PBA BIR are set to zero by software to form a 32-bit qword-aligned offset. This field is read-only after being programmed.

PBA BAR indicator 0

Specifies the function Base Address registers, located beginning at 0x10 in Configuration Space, that maps the VF MSI-X PBA into memory space. This field is read-only in the MSI-X Capability Structure.