Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 10/06/2023
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6.4. Analog Parameters (F-Tile MCDMA IP Only)

Figure 38. Analog Parameters Tab (F-Tile MCDMA IP Only)
Table 91.  Analog Parameters Tab (F-Tile MCDMA IP Only)
Parameter Value Default Value Description
Enable PCIe low loss DISABLE/ENABLE DISABLE

When you select ENABLE, the parameter enables the transceiver analog settings for low loss PCIe design.

This parameter should only be enabled for chip-to-chip design where the insertion loss from endpoint silicon pad to root port silicon pad including the package insertion loss is below 8 dB at 8 GHz.