Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 10/06/2023

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3.4.1. Endpoint MSI Support through BAS

MSI enables a device Function to request service by writing a system-specified data value to a system-specified address using a single dword Memory Write transaction. System software initializes the message address and message data (referred to as the “vector”) during device configuration, allocating one or more vectors to each MSI-capable Function.

When you enable MSI Capability in Endpoint BAS or BAM+BAS mode, the IP core exposes MSI request interface to user logic. When user issues an MSI request through this interface, internal Interrupt Controller receives inputs such as function number and MSI number from user logic and generates AVMM Write to the BAS module as shown in the figure below. The BAS receives MSI signaling from interrupt controller and generating an MSI.

Figure 9. MSI Interrupt
Note: Endpoint MSI Interrupt is only available for P-Tile MCDMA IP, F-Tile MCDMA IP and R-Tile MCDMA IP (for Port 1 and Port 2 in Endpoint Mode). H-Tile MCDMA IP does not support MSI Interrupt feature.