Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 10/06/2023
Public

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6.2.5. MCDMA Settings

Figure 35. MCDMA Settings Parameters
Table 88.  MCDMA Settings
Parameter Value Default Value Description

BAR2 Address Width

128 Bytes - 8 Bytes

4 Mbytes – 22 bits

Address width for PIO AVMM port. Default address width is 22 bits

User Mode

Multi channel DMA

Bursting Master

Bursting Slave

BAM+BAS

BAM+MCDMA

BAM+BAS+MCDMA

Data Mover Mode only

Multi channel DMA

This option allows user to configure the mode of operation for MCDMA IP. MCDMA mode has the DMA functionality. BAM and BAS offer Bursting Master and Slave AVMM capabilities without DMA functionality

Note: In R-Tile 4x4, Port 2 and 3 only support BAM, BAS and BAM+BAS user mode.

Interface type

AVMM

AVST

AVMM

User logic interface type for D2HDM and H2DDM.

Default: Avalon-MM Interface

Number of ports

1

1

Number of ports for AVMM and AVST interface is 1.

Enable User-MSIX

On / Off

Off

User MSI-X is enables user application to initiate interrupts through MCDMA, this option is available only if the user selects MCDMA mode

Enable User-FLR

On / Off

Off

User FLR, interface allows passing of FLR signals to the user side application

D2H Prefetch channels

8

16

32

64

128

256

8

Sets the D2H Prefetch channels

In the current release, the D2H Prefetch Channels parameter follows the total number of DMA channels that you select in the IP Parameter Editor up to 256 total channels. When the total number of channels selected is greater than 256, then D2H Prefetch channels are automatically fixed to 64.

Note: This parameter applicable to AVST 1 port interface only.

Maximum Descriptor Fetch

16

32

64

16

Sets the maximum descriptors that are fetched per D2H prefetch channel.

Note: This parameter is applicable to AVST 1 port interface only.

Enable Metadata

On / Off

Off

Enables Metadata

Note: This parameter is only available when the Interface Type is set to AVST.

Enable Configuration Intercept Interface

On / Off

Off

Select to enable configuration intercept interface.

Enable 10-bit tag support

On / Off

Off

This parameter is available for the following user modes: MCDMA, Bursting Slave, BAM+BAS, BAM+MCDMA and BAM+BAS+MCDMA

Note: This parameter is not supported for R-tile. 10-bit tag is set to On by the IP.

Enable address byte aligned transfer

On / Off

Off

This is the option to enable the Byte aligned address mode support needed for Kernel or DPDK drivers and DMA makes no assumption on the alignment of data w.r.t to address.

Note: This parameter is only available when the Interface Type is set to AVST.

Enable MSI Capability

On / Off

Off

Enables or disables MSI capability for BAS.

Note: This parameter is only available when User Mode is set to BAS or BAM+BAS.

Enable MSI 64-bit addressing

On / Off

Off

Enables or disables 64-bit MSI addressing.

Number of MSI Messages Requested

1

2

4

8

16

32

1

Sets the number of messages that the application can request in the multiple message capable field of the Message Control register.

Enable MSI Extended Data Capability

On / Off

Off

Enables or disables MSI extended data capability.

Export pld_warm_rst_rdy and link_req_rst_n interface to top level

On / Off

Off

Exports pld_warm_rst_rdy and link_req_rst_n interface to top level.

Note: This parameter is not available in R-Tile MCDMA IP.
Table 89.  Root Port MCDMA Settings ATT Parameters
Parameter Value Default Value Description

Enable ATT

On / Off

Off

Enables ATT for BAS

ATT Table Address Width

1 - 9

3

Sets depth of ATT. Depth is equal to 2 to the power of number entered.

ATT Window Address Width

10 - 63

16

Sets the number of BAS address bits to be used directly.