Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 10/06/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.5.1. PCIe1 Configuration, Debug and Extension Options

Figure 39. PCIe1 Configuration, Debug and Extension Options
Table 92.  PCIe1 Configuration, Debug and Extension Options Settings Table
Parameter Value Default Value Description

Port 1 REFCLK init active (only P-Tile)

On / Off

On

If this parameter is On (default), the refclk1 is stable after pin_perst and is free-running. This parameter must be set to On for Type A/B/C systems.

If this parameter is Off, refclk1 is only available later in User Mode. This parameter must be set to Off for Type D systems.

This parameter is only available in the PCIe1 Settings tab for a 2x8 topology.

For more details regarding the link subdivision feature and its usage, refer to P-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide Appendix E.