Multi Channel DMA Intel® FPGA IP for PCI Express* User Guide

ID 683821
Date 10/06/2023
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4.7. MSI Interface

Note: MSI Interface is supported only in EP mode.
Table 46.  MSI Interface Signals
Signal Name I/O Type Description
msi_req_i Input

MSI request signal.

Assertion causes Mem Write TLP to be generated on the AVST interface to the HIP based on the MSI Capability register values and other MSI input ports.

You can deassert MSI request any time after Ack (msi_ack_o) has been asserted.

msi_func_num_i[2:0] Input

Specifies the function number requesting an MSI transmission

msi_num_i[4:0] Input

MSI number that indicates the offset between the base message data and the MSI to send.

When multiple message mode is enabled, this signal sets the lower five bits of the MSI Data register. For more information, refer to PCIe base specification.

msi_ack_o Output

Ack for MSI request. Asserted for 1 clock cycle.

Your logic can deassert the MSI request as soon as this signal is asserted.

msi_status_o[1:0] Output
Indicates the execution status of requested MSI. Valid when msi_ack_o is asserted.
  • 00: MSI message sent
  • 01: Pending bit is set and no message sent (MSI is masked)
  • 10: Error (MSI is not enabled or not allocated)
  • 11: Reserved