Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/11/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.1.7. User MSI-X

User MSI-X is arbitrated along with the H2D/D2H MSI-X/Writeback requests, and is handled exactly the same way as the others post the arbitration. The high-level diagram for the MSI-X handling mechanism is shown below.

Each DMA Channel is allocated 4 MSI-X vectors:
  • 2’b00: H2D DMA Vector
  • 2’b01: H2D Event Interrupt
  • 2’b10: D2H DMA Vector
  • 2’b11: D2H Event Interrupt

2’b00 and 2’b10 to address the Descriptor completion related interrupts (DMA operation MSI-X) on both the paths.

2’b01 and 2’b11 are used for user MSI-X.

Note: msix_queue_dir Queue direction. D2H = 0, H2D =1