7.4.1. Required Supporting IP
Intel® Stratix® 10 and Intel Agilex® 7 devices use a parallel, sector-based architecture that distributes the core fabric logic across multiple sectors. Device configuration proceeds in parallel with each Local Sector Manager (LSM) configuring its own sector. Consequently, FPGA registers and core logic are not released from reset at exactly the same time, as has always been the case in previous families.
In order to keep application logic held in the reset state until the entire FPGA fabric is in user mode, Intel® Stratix® 10 and Intel Agilex® 7 devices require you to include the Intel® Stratix® 10 Reset Release IP.
Refer to the Multi Channel DMA for PCI Express IP design example to see how the Reset Release IP is connected with the Multi Channel DMA for PCI Express IP component.
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