Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/11/2023
Document Table of Contents

1.2. Known Issues

The following summarizes known issues in the current IP release:
  1. MCDMA AVMM PIO may drop Posted Writes when user logic backpressures by asserting rx_pio_waitrequest_i
  2. Multichannel D2H AVST configuration has stability issues when total number of D2H channels configured is greater than 256
  3. Per vector masking capability for User Event MSI-X is not supported in MCDMA IP Intel® Quartus® Prime 23.1 release.
  4. Design Example simulation in Intel® Quartus® Prime 23.1 release is failing for BAM+BAS+MCDMA user mode in H-Tile, when SRIOV is enabled.
  5. MCDMA R-Tile Design Example simulations are not supported in Intel® Quartus® Prime 23.1 release, except for PIO using MCDMA Bypass Mode Design Example. Simulations only supported in VCS* / VCS* MX simulators.
  6. Avalon-ST Source (H2D) interface data can get corrupted, if a Completion timeout event occurrs for H2DDM descriptor fetch. This issue happens only if the SOP descriptor is fetched successfully and the EOP descriptor for a channel got missed because of the Completion timeout event.
  7. In Ubuntu 22.04 LTS Operating System, MCDMA custom driver gets stuck failing Tx & Rx queues when Virtual Function I/O (VFIO) kernel module and MSIX mode are set.
Note: These issues may be addressed in a future release of Intel® Quartus® Prime software.

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