Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/11/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5. Parameters (H-Tile)

This chapter provides a reference for all the H-Tile parameters of the Multi Channel DMA IP for PCI Express.

Table 56.  Design Environment ParameterStarting in Intel® Quartus® Prime 18.0, there is a new parameter Design Environment in the parameters editor window.

Parameter

Value

Description

Design Environment

Standalone

System

Identifies the environment that the IP is in.

  • The Standalone environment refers to the IP being in a standalone state where all its interfaces are exported.
  • The System environment refers to the IP being instantiated in a Platform Designer system.