Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/11/2023
Public

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Document Table of Contents

6.2.1. Base Address Register

Note: This tab is only available for Bursting Master, Bursting Slave, BAM+BAS, BAM+MCDMA, BAM+BAS+MCDMA and Data Mover Only user modes. This tab is not available when only MCDMA user mode is selected. Options of setting BAR0/BAR1 Type is not available if MCDMA is selected with BAM.
Table 70.  Base Address Registers
Parameter Value Description
BAR0 Type

Disabled

64-bit prefetchable memory

64-bit non-prefetchable memory

32-bit non-prefetchable memory

If you select 64-bit prefetchable memory, 2 contiguous BARs are combined to form a 64-bit prefetchable BAR; you must set the higher numbered BAR to Disabled.

Defining memory as prefetchable allows contiguous data to be fetched ahead. Prefetching memory is advantageous when the requestor may require more data from the same region than was originally requested. If you specify that a memory is prefetchable, it must have the following 2 attributes:
  • Reads do not have side effects such as changing the value of the data read.
  • Write merging is allowed.
BAR1 Type

Disabled

32-bit non-prefetchable memory

For a definition of prefetchable memory, refer to the BAR0 Type description.

BAR2 Type

Disabled

64-bit prefetchable memory

64-bit non-prefetchable memory

32-bit non-prefetchable memory

For a definition of prefetchable memory and a description of what happens when you select the 64-bit prefetchable memory option, refer to the BAR0 Type description.

BAR3 Type

Disabled

32-bit non-prefetchable memory

For a definition of prefetchable memory, refer to the BAR0 Type description.

BAR4 Type

Disabled

64-bit prefetchable memory

64-bit non-prefetchable memory

32-bit non-prefetchable memory

For a definition of prefetchable memory and a description of what happens when you select the 64-bit prefetchable memory option, refer to the BAR0 Type description.

BAR5 Type

Disabled

32-bit non-prefetchable memory

For a definition of prefetchable memory, refer to the BAR0 Type description.

BARn Size 128 Bytes - 16 EBytes

Specifies the size of the address space accessible to BARn when BARn is enabled.

n = 0, 1, 2, 3, 4 or 5

Expansion ROM

Disabled

4 KBytes - 12 bits

8 KBytes - 13 bits

16 KBytes - 14 bits

32 KBytes - 15 bits

64 KBytes - 16 bits

128 KBytes - 17 bits

256 KBytes - 18 bits

512 KBytes - 19 bits

1 MByte - 20 bits

2 MBytes - 21 bits

4 MBytes - 22 bits

8 MBytes - 23 bits

16 MBytes - 24 bits

Specifies the size of the expansion ROM from 4 KBytes to 16 MBytes when enabled.