Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/11/2023

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Document Table of Contents

8.1.4. Software Flow

Figure 46. Multi Channel DMA IP for PCI Express Software Operation Flow

Step 1

  • Application creates the thread based on the required port of a channel
  • After spawning the thread, the thread tries to acquire the available channel’s port. In case if all channels ports are busy thread waits in poll mode
  • In the context of thread, libqdma allocates descriptors buffer memory in the host
  • libqdma initializes following registers in QCSR associates with queue, which includes Starting address of descriptors, queue size, write back address for Consumed Head, payload size in D2H descriptors and then enables the channels
QCSR registers:
  • Q_RESET (offset 8’h48)
  • Q_TAIL_POINTER (offset 8’h14) Set 0
  • Q_START_ADDR_L (Offset 8’h08)
  • Q_START_ADDR_H (Offset 8’h0C)
  • Q_SIZE (Offset 8’h10)
  • Q_CONSUMED_HEAD_ADDR_L (Offset 8’h20)
  • Q_CONSUMED_HEAD_ADDR_H (Offset 8’h24)
  • Q_BATCH_DELAY (Offset 8’h28)
  • Set q_en, q_wb/intr_en bits Q_CTRL (Offset 8’h00)
  • (Q_PYLD_COUNT) (Offset 8'h44)
GCSR register:
  • WB_INTR_DELAY (Offset 8’h08)

Step 2

  • Threads continuously try to send/receive the data and library keeps checking if channel is busy or descriptor ring is full
  • If channel is not busy and descriptor ring is not full it goes to step 3. If channel is busy or descriptors ring is full thread retries to initiate the transfer again
Descriptor ring full is identified by checking the Consumed Head and Tail pointer registers.

Step 3

Thread requests for new descriptor to submit the request and updates the required field i.e. descriptor index, SOF, EOF, Payload, MSI-X enable and writeback enable.

Step 4

After initializing descriptor ring buffer, the libqdma writes number of descriptor updates into tail register of QCSR region. On every descriptor update the tail pointer is increased by 1.

QCSR tail pointer register: Q_TAIL_POINTER (Offset 8’h14)

Step 5

  • Once the tail pointer write happens, Multi Channel DMA IP for PCI Express fetches descriptors from host memory starting from the programmed Q_START_ADDR_L/H address
  • Multi Channel DMA IP for PCI Express parses the descriptor content to find the sources, destination addresses and length of the data from descriptor and starts DMA operation

Step 6

Once descriptor processing is completed, IP notifies the completion status based on following methods, which can be enabled in each descriptor.
  • Either based on MSI-X Interrupt : Multi Channel DMA IP for PCI Express sends MSI-X interrupt to host if enabled in Q_CTRL.
  • Writeback: Multi Channel DMA for PCI Express IP updates Q_CONSUMED_HEAD_ADDR_L/H, if writeback is enabled in Q_CTRL.