Multi Channel DMA Intel® FPGA IP for PCI Express User Guide

ID 683821
Date 4/11/2023
Public

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Document Table of Contents

6.2.4.2. PCIe0 Link

Table 75.  PCIe0 Link

Parameter

Value

Default Value

Description

Link port number (Root Port only)

0-255

1

Sets the read-only value of the port number field in the Link Capabilities register. This parameter is for Root Ports only. It should not be changed.

Slot clock configuration

On/Off On

When you turn this option On, indicates that the Endpoint uses the same physical reference clock that the system provides on the connector.

When Off, the IP core uses an independent clock regardless of the presence of a reference clock on the connector. This parameter sets the Slot Clock Configuration bit (bit 12) in the PCI Express Link Status register.

You cannot enable this option when the Enable SRIS Mode option is enabled.

Enable Modified TS

On/Off On

Enables the controller to send the Modified TS OS if both sides of the link agree when the SUPPORT_MOD_TS register is set to 1.

If the port negotiates alternate protocols or passes a Training Set Message, the bit must be set to 1.

Note: This feature is only supported for R-Tile.