Ethernet Toolkit User Guide

ID 683793
Date 4/01/2024
Document Table of Contents

3.1.3. Settings

This feature is only available for E-tile Ethernet IPs.

For the E-Tile Hard IP for Ethernet Intel® FPGA IP and E-Tile Ethernet IP for Intel Agilex® 7 FPGA, the Settings group allows you to select the number of channels you want to access in case of multi-channel 10G/25G design. In case of Low Latency 40G Ethernet Intel FPGA IP and Low Latency 100G Ethernet Intel FPGA IP, you should see a text box that allow you to set the value of clk_status signal. This value is being used in calculation of TX and RX clock values.

Figure 20. Example of Settings Group