Ethernet Toolkit User Guide

ID 683793
Date 3/28/2022
Public
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Document Table of Contents
Document Table of Contents
1. Ethernet Toolkit Overview 2. Setting up the Ethernet Toolkit 3. Functional Description 4. Document Revision History for the Ethernet Toolkit User Guide
1. Ethernet Toolkit Overview
1.1. Features 1.2. Supported Ethernet IP Cores and Devices
2. Setting up the Ethernet Toolkit
2.1. System Requirements and Prerequisites 2.2. Running the Ethernet Toolkit
2.1. System Requirements and Prerequisites
2.1.1. System Requirements 2.1.2. Enabling your Design for the Ethernet Toolkit
3. Functional Description
3.1. Ethernet Toolkit Groups and Tabs 3.2. Link Bring Up Guidelines
3.1. Ethernet Toolkit Groups and Tabs
3.1.1. IP Configuration and Other Information 3.1.2. General Commands 3.1.3. Settings 3.1.4. Status 3.1.5. Statistics Counters 3.1.6. Testing Features
3.1.4. Status
3.1.4.1. Link Bring Up 3.1.4.2. PCS Status 3.1.4.3. PHY Status 3.1.4.4. MAC Settings 3.1.4.5. AN and LT Status
3.1.5. Statistics Counters
3.1.5.1. Example Design Packet Generator Settings 3.1.5.2. Transmitter and Receiver Statistics 3.1.5.3. RS-FEC
3.1.5.1. Example Design Packet Generator Settings
3.1.5.1.1. Packet Generator for E-, H-, and L-tile Ethernet IPs 3.1.5.1.2. Packet Generator for F-tile Ethernet IP
3.1.6. Testing Features
3.1.6.1. Example Design PHY and Packet Generator Loopback Test 3.1.6.2. Read Register 3.1.6.3. Write to Register
3.2. Link Bring Up Guidelines
3.2.1. Example Link Bring Up using E-Tile Hard IP 3.2.2. Example Link Bring Up using F-Tile Ethernet Intel® FPGA Hard IP
1. Ethernet Toolkit Overview
2. Setting up the Ethernet Toolkit
3. Functional Description
4. Document Revision History for the Ethernet Toolkit User Guide

3.1.3. Settings

This feature is only available for E-tile Ethernet IPs.

For the E-Tile Hard IP for Ethernet Intel® FPGA IP and E-Tile Hard IP for Intel Agilex FPGA IP, the Settings group allows you to select the number of channels you want to access in case of multi-channel 10G/25G design. In case of Low Latency 40G Ethernet Intel FPGA IP and Low Latency 100G Ethernet Intel FPGA IP, you should see a text box that allow you to set the value of clk_status signal. This value is being used in calculation of TX and RX clock values.

Figure 10. Example of Settings Group
Level Two Title

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