Ethernet Toolkit User Guide

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ID 683793
Date 1/10/2023
Public
Document Table of Contents
Document Table of Contents
1. Ethernet Toolkit Overview 2. Setting up the Ethernet Toolkit 3. Functional Description 4. Document Revision History for the Ethernet Toolkit User Guide
1. Ethernet Toolkit Overview
1.1. Features 1.2. Supported Ethernet IP Cores and Devices
2. Setting up the Ethernet Toolkit
2.1. System Requirements and Prerequisites 2.2. Running the Ethernet Toolkit
2.1. System Requirements and Prerequisites
2.1.1. System Requirements 2.1.2. Enabling your Design for the Ethernet Toolkit
3. Functional Description
3.1. Ethernet Toolkit Groups and Tabs 3.2. Link Bring Up Guidelines
3.1. Ethernet Toolkit Groups and Tabs
3.1.1. IP Configuration and Other Information 3.1.2. General Commands 3.1.3. Settings 3.1.4. Status 3.1.5. Statistics Counters 3.1.6. Testing Features
3.1.4. Status
3.1.4.1. Link Bring Up 3.1.4.2. PCS Status 3.1.4.3. PHY Status 3.1.4.4. MAC Settings 3.1.4.5. AN and LT Status
3.1.5. Statistics Counters
3.1.5.1. Example Design Packet Generator Settings 3.1.5.2. Transmitter and Receiver Statistics 3.1.5.3. RS-FEC
3.1.5.1. Example Design Packet Generator Settings
3.1.5.1.1. Packet Generator for E-, H-, and L-tile Ethernet IPs 3.1.5.1.2. Packet Generator for F-tile Ethernet IP
3.1.6. Testing Features
3.1.6.1. Example Design PHY and Packet Generator Loopback Test 3.1.6.2. Read Register 3.1.6.3. Write to Register
3.2. Link Bring Up Guidelines
3.2.1. Example Link Bring Up using E-Tile Hard IP 3.2.2. Example Link Bring Up using F-Tile Ethernet Intel® FPGA Hard IP
1. Ethernet Toolkit Overview
2. Setting up the Ethernet Toolkit
3. Functional Description
4. Document Revision History for the Ethernet Toolkit User Guide

3.1.6.1. Example Design PHY and Packet Generator Loopback Test

You can access Example Design PHY and Packet Generator Loopback Test tab only if you are using an Intel® Quartus® Prime generated design example. To use this tab of the Ethernet Toolkit, you must disable MAC Loopback Mode option in Example Design Packet Generator Settings group under Statistics Counter tab.
When you turn on the Run Test in External Loopback Mode option, the internal serial loopback is disabled for the IP. When you turn on the Start PHY and Packet Generator Loopback Test option, the test procedure runs a series of processes as shown in the figure below.
Figure 27. Example Design PHY and Packet Generator Loopback Test
Level Two Title

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