Ethernet Toolkit User Guide

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ID 683793
Date 1/10/2023
Public
Document Table of Contents
Document Table of Contents
1. Ethernet Toolkit Overview 2. Setting up the Ethernet Toolkit 3. Functional Description 4. Document Revision History for the Ethernet Toolkit User Guide
1. Ethernet Toolkit Overview
1.1. Features 1.2. Supported Ethernet IP Cores and Devices
2. Setting up the Ethernet Toolkit
2.1. System Requirements and Prerequisites 2.2. Running the Ethernet Toolkit
2.1. System Requirements and Prerequisites
2.1.1. System Requirements 2.1.2. Enabling your Design for the Ethernet Toolkit
3. Functional Description
3.1. Ethernet Toolkit Groups and Tabs 3.2. Link Bring Up Guidelines
3.1. Ethernet Toolkit Groups and Tabs
3.1.1. IP Configuration and Other Information 3.1.2. General Commands 3.1.3. Settings 3.1.4. Status 3.1.5. Statistics Counters 3.1.6. Testing Features
3.1.4. Status
3.1.4.1. Link Bring Up 3.1.4.2. PCS Status 3.1.4.3. PHY Status 3.1.4.4. MAC Settings 3.1.4.5. AN and LT Status
3.1.5. Statistics Counters
3.1.5.1. Example Design Packet Generator Settings 3.1.5.2. Transmitter and Receiver Statistics 3.1.5.3. RS-FEC
3.1.5.1. Example Design Packet Generator Settings
3.1.5.1.1. Packet Generator for E-, H-, and L-tile Ethernet IPs 3.1.5.1.2. Packet Generator for F-tile Ethernet IP
3.1.6. Testing Features
3.1.6.1. Example Design PHY and Packet Generator Loopback Test 3.1.6.2. Read Register 3.1.6.3. Write to Register
3.2. Link Bring Up Guidelines
3.2.1. Example Link Bring Up using E-Tile Hard IP 3.2.2. Example Link Bring Up using F-Tile Ethernet Intel® FPGA Hard IP
1. Ethernet Toolkit Overview
2. Setting up the Ethernet Toolkit
3. Functional Description
4. Document Revision History for the Ethernet Toolkit User Guide

3.1.4.5. AN and LT Status

The AN and LT features are supported by both example and non-example designs.
To enable AN and LT along with Ethernet IP, select the Enable auto-negotiation and link training checkbox in the Ethernet Hard IP GUI.
Figure 16. Enable AN and LT

The Ethernet Toolkit displays AN/LT status in the IP Configuration and Other Information tab as shown in the figure below.

Figure 17.  IP Configuration and Other Information Tab
A new sub tab named AN/LT Status is added at the bottom of the Status tab displaying AN/LT features.
Figure 18. Status Tab for Ethernet Toolkit and AN/LT Status Sub Tab
The AN/LT Status section shown above contains a number of checkboxes as listed below.
  • Reset AN/LT Sequencer—Resets the AN/LT sequencer.
  • Ignore Nonce Field During AN—Needs to be selected when the F-tile is connected in loopback mode.
  • Disable Link Fail Timer—Disables the Link Fail Timer when selected.
  • Disable Max Wait Timer—Disables the Max Wait Timer when selected.
  • Refresh—Updates all the registers data when pressed.
  • KR Pause—Pauses the KR CPU when selected.
  • SEQ Force Mode—Not supported in the current Release.
The AN/LT Status tab contains 4 different tabs:
  1. AN/LT Status—Displays the register status information of both AN and LT, which includes the following:
    1. LT Status Per Lane (if design supports multi lanes)
    2. LP Base Page details
    3. LP Next Page details
    4. Information about the value of a few AN/ LT status registers
    Figure 19. AN/LT Status Tab
  2. AN/LT Config—This sub tab includes AN and LT configuration registers. which the user can enable or disable.
    1. Enable AN—Enables AN when selected; disables AN when unselected.
    2. AN Enabled—Displays whether AN is enabled or not.
    3. Enable LT—Enables LT when selected; disables LT when unselected.
    4. LT Enabled—Displays whether LT is enabled or not.
    5. Reset AN—Resets all state machines.
    Figure 20. AN/LT Config Tab
  3. Link Analysis—This sub tab is used for Link Analysis. It takes a csv file with Signal Tap data as an input and displays the Time Delta for different KR/ANLT states.
    1. Users must tap the kr_debug_0 signal from the signal tap analyser then converting the .STP file into the csv format to use this tab.
    2. If the tool doesn’t find the kr_debug_0 signal data from the csv file, then it displays the error “Required Signals Not Found”.
    3. Based on data in the csv file, the tool calculates the number of samples captured.
    4. Users can check the individual data for each sample by selecting the sample number from the dropdown menu.
    5. The tool shows data for Auto_Neg states, Link_Training States, and Data Mode States.
    Figure 21. Link Analysis Tab
  4. Read Register—This sub tab is used to dump all available register data into a csv file.
    1. It reads the data from the board when users click on “Press to Export Reg Data”.
    2. The tool captures dynamic data.
    3. The csv file includes the Register Name, Bit Name, Bit Value, and Description of the Bit columns.
    4. Users must provide a csv file as an input into which data can be dumped.
    Figure 22. Read Register Tab
Table 2.  Sample Data from Dumped CSV File
Register Name Field Name Field Value Field Description
seq_cfg kr_pause 0
Pauses ANLT function
  • 1: ANLT function is paused when bit 0xB1[31] is high
  • 0: Normal ANLT function

Set this bit before accessing PMA registers via the xcvr reconfig interface to ensure no conflict with the ANLT function.
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