Ethernet Toolkit User Guide

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ID 683793
Date 4/28/2025
Public
Document Table of Contents
Document Table of Contents x
1. Ethernet Toolkit Overview 2. Setting up the Ethernet Toolkit 3. Functional Description 4. Document Revision History for the Ethernet Toolkit User Guide
1. Ethernet Toolkit Overview x
1.1. Features 1.2. Supported Ethernet IP Cores and Devices
2. Setting up the Ethernet Toolkit x
2.1. System Requirements and Prerequisites 2.2. Running the Ethernet Toolkit
2.1. System Requirements and Prerequisites x
2.1.1. System Requirements 2.1.2. Enabling your Design for the Ethernet Toolkit
3. Functional Description x
3.1. Ethernet Toolkit Groups and Tabs 3.2. Link Bring Up Guidelines 3.3. Ethernet Toolkit Multirate Support 3.4. Ethernet Toolkit Subsystem Support 3.5. Ethernet Toolkit GTS Ethernet Hard IP Support
3.1. Ethernet Toolkit Groups and Tabs x
3.1.1. IP Configuration and Other Information 3.1.2. General Commands 3.1.3. Settings 3.1.4. Status 3.1.5. Statistics Counters 3.1.6. Testing Features
3.1.2. General Commands x
3.1.2.1. Loopback 3.1.2.2. Resets
3.1.4. Status x
3.1.4.1. Link Bring Up 3.1.4.2. PCS Status 3.1.4.3. PHY Status 3.1.4.4. MAC Settings 3.1.4.5. AN and LT Status
3.1.5. Statistics Counters x
3.1.5.1. Example Design Packet Generator Settings 3.1.5.2. Transmitter and Receiver Statistics 3.1.5.3. RS-FEC
3.1.5.1. Example Design Packet Generator Settings x
3.1.5.1.1. Packet Generator for E-, H-, and L-Tile Ethernet IPs 3.1.5.1.2. Packet Generator for F-Tile Ethernet IP
3.1.5.2. Transmitter and Receiver Statistics x
3.1.5.2.1. Effective Bandwidth Calculation
3.1.5.3. RS-FEC x
3.1.5.3.1. 32-Bit Soft CWBIN Counter Status
3.1.6. Testing Features x
3.1.6.1. Example Design PHY and Packet Generator Loopback Test 3.1.6.2. Read Register 3.1.6.3. Write to Register
3.2. Link Bring Up Guidelines x
3.2.1. Example Link Bring Up Using E-Tile Hard IP 3.2.2. Example Link Bring Up Using F-Tile Hard IP 3.2.3. Example Link Bring Up Using GTS Ethernet Hard IP
1. Ethernet Toolkit Overview
2. Setting up the Ethernet Toolkit
3. Functional Description
4. Document Revision History for the Ethernet Toolkit User Guide

3.1.4.5. AN and LT Status

The AN and LT features are supported for example and your custom designs in Quartus® Prime Pro Edition software version 23.3 onwards.
Note: Serial loopback is not supported for AN/LT with FHT PMA.

To enable AN and LT along with Ethernet IP, select the Enable auto-negotiation and link training checkbox in the Ethernet Hard IP GUI.

To enable the Ethernet Toolkit for your custom design, you must enable the Enable AN/LT Debug Endpoint for Ethernet toolkit checkbox in the F-Tile Auto-Negotiation and Link Training for Ethernet Intel FPGA IP GUI as shown in the following figure.
Figure 25. Enable Ethernet Toolkit for F-Tile Auto-Negotiation and Link Training for Ethernet Intel FPGA IP

The Ethernet Toolkit displays AN/LT status in the IP Configuration and Other Information tab as shown in the figure below.

Figure 26.  IP Configuration and Other Information Tab
A new sub tab named AN/LT Status is added at the bottom of the Status tab displaying AN/LT features.
Figure 27. Status Tab for Ethernet Toolkit and AN/LT Status Sub Tab
The AN/LT Status section shown above contains a number of checkboxes as listed below.
  • Reset AN/LT Sequencer—Resets the AN/LT sequencer.
  • Ignore Nonce Field During AN—Needs to be selected when the F-tile is connected in loopback mode.
  • Disable Link Fail Timer—Disables the Link Fail Timer when selected.
  • Disable Max Wait Timer—Disables the Max Wait Timer when selected.
  • Refresh—Updates all the registers data when pressed.
  • KR Pause—Pauses the KR CPU when selected.
  • SEQ Force Mode—Not supported in the current Release.
The AN/LT Status tab contains 4 different tabs:
  1. AN/LT Status—Displays the register status information of both AN and LT, which includes the following:
    1. LT Status Per Lane (if design supports multi lanes)
    2. LP Base Page details
    3. LP Next Page details
    4. Information about the value of a few AN/ LT status registers
    Figure 28. AN/LT Status Tab
  2. AN/LT Config—This sub tab includes AN and LT configuration registers. which the user can enable or disable.
    1. Enable AN—Enables AN when selected; disables AN when unselected.
    2. AN Enabled—Displays whether AN is enabled or not.
    3. Enable LT—Enables LT when selected; disables LT when unselected.
    4. LT Enabled—Displays whether LT is enabled or not.
    5. Reset AN—Resets all state machines.
    Figure 29. AN/LT Config Tab
  3. Link Analysis—This sub tab is used for Link Analysis. It takes a csv file with Signal Tap data as an input and displays the time delta for different KR/AN/LT states.
    1. You must tap the kr_debug_0 signal for the AN/LT instances and ports from the signal tap analyzer tool.
    2. Convert the .STP file data into the csv format and save it into a file.
    3. You must upload the converted csv file into the tool and click the Start Analysis button.
    4. If the tool does not find the kr_debug_0 signal data from the csv file, then it displays the error Required Signals Not Found.
    5. Based on data in the csv file, the tool calculates the number of samples captured (iterations of AN/LT sequence) for each port and AN/LT instance.
    6. You can check the data for each sample by selecting the AN/LT instance, port instance, and the sample (iteration) number from the dropdown menu options. You must press the Display Sample button after selecting from the dropdown list.
    7. The tool shows the data for Auto negotiation states, Link training states, and Data mode states.
    Figure 30. Link Analysis Tab
  4. Read Register—This sub tab is used to dump all available register data into a csv file.
    1. It reads the data from the board when users click on Press to Export Reg Data.
    2. The tool captures dynamic data.
    3. The csv file includes the Register Name, Bit Name, Bit Value, and Description of the Bit columns.
    4. Users must provide a csv file as an input into which data can be dumped.
    Figure 31. Read Register Tab
Table 3.  KR_Pause Register
Register Name Field Name Field Value Field Description
seq_cfg kr_pause 0
Pauses AN/LT function
  • 1: AN/LT function is paused when bit 0xB1[31] is high
  • 0: Normal AN/LT function

Set this bit before accessing PMA registers via the transceiver reconfig interface to ensure no conflict with the AN/LT function. Also, you must set this bit (kr_pause) before starting the PRBS generator in the Transceiver Toolkit (TTK).

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