Visible to Intel only — GUID: dsf1596653006401
Ixiasoft
1.2. Supported Ethernet IP Cores and Devices
| Supported Ethernet IP Cores | Supported Tile | Supported Device | Initial Supported Intel® Quartus® Prime Version | Initial Supported IP Version |
|---|---|---|---|---|
| Intel® Stratix® 10 10GBASE-KR PHY IP | L- and H-tile | Intel® Stratix® 10 | 20.1 | 19.1.0 |
| Low Latency 40G Ethernet Intel® FPGA IP | L- and H-tile | Intel® Stratix® 10 | 20.1 | 19.1.0 |
| Low Latency 100G Ethernet Intel® FPGA IP | L- and H-tile | Intel® Stratix® 10 | 20.1 | 19.1.1 |
| H-Tile Hard IP for Ethernet Intel® FPGA IP | H-tile | Intel® Stratix® 10 | 20.1 | 19.2.0 |
| Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP | H-tile | Intel® Stratix® 10 GX 10M | 20.1 | 19.1.0 |
| E-Tile Hard IP for Ethernet Intel® FPGA IP | E-tile | Intel® Stratix® 10 | 20.1 | 19.3.0 |
| E-Tile Ethernet IP for Intel Agilex FPGA | E-tile | Intel® Agilex™ | 20.1 | 19.3.0 |
| Low Latency E-Tile 40G Ethernet Intel® FPGA IP | E-tile | Intel® Stratix® 10 | 20.1 | 19.1.0 |
| Intel® Agilex™ | ||||
| F-Tile Ethernet Intel® FPGA Hard IP 1 | F-tile | Intel® Agilex™ | 21.3 | 3.0.0 |
1 The Ethernet Toolkit is not available for the multi-instance IP design examples.
Did you find the information on this page useful?
Feedback Message
Characters remaining: