Ethernet Toolkit User Guide

ID 683793
Date 4/01/2024
Public
Document Table of Contents

1.2. Supported Ethernet IP Cores and Devices

Table 1.  Ethernet Toolkit Supported IP Cores, Devices, and Tiles
Supported Ethernet IP Cores Supported Tile Supported Device Initial Supported Quartus® Prime Version Initial Supported IP Version
Stratix® 10 10GBASE-KR PHY IP L- and H-Tile Stratix® 10 20.1 19.1.0
Low Latency 40G Ethernet Intel® FPGA IP L- and H-Tile Stratix® 10 20.1 19.1.0
Low Latency 100G Ethernet Intel® FPGA IP L- and H-Tile Stratix® 10 20.1 19.1.1
H-Tile Hard IP for Ethernet Intel® FPGA IP H-Tile Stratix® 10 20.1 19.2.0
Low Latency 40G for ASIC Proto Ethernet Intel® FPGA IP H-Tile Stratix® 10 GX 10M 20.1 19.1.0
E-Tile Hard IP for Ethernet Intel® FPGA IP E-Tile Stratix® 10 20.1 19.3.0
E-Tile Ethernet IP for Intel Agilex® 7 FPGA E-Tile Agilex™ 7 20.1 19.3.0
Low Latency E-Tile 40G Ethernet Intel® FPGA IP E-Tile Stratix® 10 20.1 19.1.0
Agilex™ 7
F-Tile Ethernet Intel® FPGA Hard IP 1 F-Tile Agilex™ 7 21.3 3.0.0
F-Tile Ethernet Subsystem Intel® FPGA IP F-Tile Agilex™ 7 23.3 23.0.0
F-Tile Ethernet Multirate Intel® FPGA IP F-Tile Agilex™ 7 23.3 23.0.0
GTS Ethernet Intel FPGA Hard IP N/A Agilex™ 5 24.1 4.0.0
1 The Ethernet Toolkit is available for the multi-instance IP design examples in Quartus® Prime software version 23.1 onwards.