2023.01.10 |
- In the section Packet Generator for F-tile Ethernet IP (3.1.5.1.2), added a note before the figure Example Design Packet Generator Settings Tab.
- Updated the figure Ethernet Toolkit Groups and Tabs for F-Tile Ethernet IPs (Figure 6 on page 9).
- Updated the section AL and LT Status (3.1.4.5).
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2022.09.20 |
In the section Packet Generator for F-tile Ethernet IP (3.1.5.1.2), made the following changes:
- Changed the "MAC Client Loopback Mode:" to "Packet Client Loopback Mode:" in the first bullet item.
- Updated Figure 18 (Example Design Packet Generator Settings Tab) on the following page.
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2022.03.28 |
Updated the Example of RS-FEC Tab figure. |
2021.10.04 |
- Globally added F-Tile Ethernet Intel® FPGA Hard IP to the list of Ethernet Toolkit supported IP cores.
- Updated existing descriptions if specific for E-Tile Ethernet IP.
- Added new GUI screenshots and descriptions for F-Tile Ethernet IP.
- Clarified the list of features supported for E-Tile Ethernet IP and F-Tile Ethernet IP
- Separated Example Design Packet Generator Settings and Link Bring-Up Guidelines section to the E-, H-, and L-tile, and F-tile subsections.
- Added new topic: Example Link Bring-Up using F-Tile Ethernet Intel® FPGA Hard IP
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2021.04.02 |
Updated Running the Ethernet Toolkit. Described a limitation for design examples with enabled auto-negotiation and link training. |
2020.09.28 |
Initial release. |
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