Ethernet Toolkit User Guide

ID 683793
Date 1/10/2023
Document Table of Contents

2.2. Running the Ethernet Toolkit

Before you begin with running the Ethernet toolkit, you must compile your Ethernet Intel FPGA IP with JTAG to Avalon Memory-Mapped master bridge parameter enabled.

Avalon® memory-mapped interface provides access to various toolkits. To avoid possible Avalon® memory-mapped interface arbitration issues, ensure only one toolkit has access to the interface at the time.

If your E-tile Ethernet IP design example has auto-negotiation and link training enabled, set 0xB0[31] register bit to 1 before accessing PMA registers via the transceiver reconfiguration interface. Read back 0xB0[31] register bit to ensure no conflict with the auto-negotiation and link training function. For register description, refer to the E-tile Hard IP User Guide.

Figure 4. Opening Ethernet Toolkit in Intel® Quartus® Prime Software

Perform the following steps to launch the Ethernet Toolkit:

  1. In the Intel® Quartus® Prime Pro Edition software, select Tools > System Debugging Tools > System Console to launch the system console.
  2. In the system console, click Load Design in the Toolkit Explorer tab, and load the generated .sof file. If you already have Intel® Quartus® Prime project containing .sof is open, you just need to launch the system console.
  3. You can see all of the Ethernet IP instances supported by Ethernet Toolkit within the design. Select one of the instances. The Ethernet Toolkit can automatically detect an instance of a supported Ethernet Intel® FPGA IP within a design.
  4. Now select the toolkit corresponding to the Ethernet IP that was selected in Details tab, and click Open Toolkit.

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