Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

ID 683780
Date 9/29/2022
Document Table of Contents

2.5.1. VREF Sources and VREF Pins

Consider these VREF pins guidelines.
  • Intel® Agilex™ devices support internal and external VREF sources.
    • There is an external VREF pin for every I/O bank, providing one external VREF source for all I/Os in the same bank.
    • Each I/O lane in the bank also has its own internal VREF generator. You can configure each I/O lane independently to use its internal VREF or the I/O bank's external VREF source. All I/O pins in the same I/O lane use the same VREF source.
  • The internal VREF is supported only for external memory interfaces.
  • You can use the internal VREF with calibration to support DDR4 using the POD12 I/O standard. You cannot mix the POD12 I/O standard with other voltage-referenced I/O standards in the same I/O lane.
  • You can place any combination of input, output, or bidirectional pins near VREF pins. There is no VREF pin placement restriction.
  • The VREF pins are dedicated for voltage-referenced single-ended I/O standards. You cannot use the VREF pins as user I/Os.
  • Connect unused VREF pins to GND.

The VREF pin leakage current is typically 0.15 uA and can go up to 8 uA.

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