6.1.5. GPIO Intel® FPGA IP Architecture
The GPIO IP supports the GPIO components and features of the Intel® Agilex™ F-Series and I-Series device family. You can use the Intel® Quartus® Prime parameter editor to configure the GPIO IP.
Components of the GPIO IP:
- Double data rate input/output (DDIO)—halves or doubles the data-rate of a communication channel
- Delay chains—configure the delay chains to perform specific delay and assist in I/O timing closure
- I/O buffers—connect the pads to the FPGA
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