Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

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ID 683780
Date 9/29/2022
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Document Table of Contents
Document Table of Contents x
1. Intel Agilex General-Purpose I/O Overview 2. Intel® Agilex™ F-Series and I-Series General-Purpose I/O Banks 3. Intel® Agilex™ HPS I/O Banks 4. Intel® Agilex™ SDM I/O Banks 5. Intel® Agilex™ I/O Troubleshooting Guidelines 6. Intel® Agilex™ General-Purpose I/O IPs 7. Programmable I/O Features Description 8. Documentation Related to the Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide 9. Document Revision History for the Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide
1. Intel Agilex General-Purpose I/O Overview x
1.1. Package Selection and I/O Vertical Migration Support 1.2. Types of I/O Banks
2. Intel® Agilex™ F-Series and I-Series General-Purpose I/O Banks x
2.1. GPIO Bank Overview 2.2. GPIO Features 2.3. GPIO Implementation Guide 2.4. Intel® Agilex™ I/O Termination 2.5. Intel® Agilex™ GPIO Design Guidelines 2.6. I/O Simulation
2.1. GPIO Bank Overview x
2.1.1. GPIO Bank Structure 2.1.2. I/O Buffers and Registers
2.2. GPIO Features x
2.2.1. Supported I/O Standards for GPIO Banks 2.2.2. GPIO Buffer Behavior 2.2.3. Programmable I/O Element Features for the GPIO Bank
2.2.3. Programmable I/O Element Features for the GPIO Bank x
2.2.3.1. Guidelines: Programmable Output Slew Rate Control 2.2.3.2. Guidelines: Programmable Open-Drain Output 2.2.3.3. Guidelines: Programmable Bus-Hold 2.2.3.4. Guidelines: Programmable Pull-Up Resistor 2.2.3.5. Guidelines: Programmable De-Emphasis
2.3. GPIO Implementation Guide x
2.3.1. I/O Assignments with the Intel® Quartus® Prime Assignment Editor 2.3.2. Assigning Pin I/O Standards in the Intel® Quartus® Prime Pin Planner
2.3.1. I/O Assignments with the Intel® Quartus® Prime Assignment Editor x
2.3.1.1. Assigning Pin I/O Standards in the Intel® Quartus® Prime Assignment Editor 2.3.1.2. Assigning Programmable IOE Features in the Intel® Quartus® Prime Assignment Editor 2.3.1.3. GPIO Programmable IOE Features Assignment Names and Settings
2.4. Intel® Agilex™ I/O Termination x
2.4.1. Single-Ended I/O Termination in Intel® Agilex™ Devices 2.4.2. True Differential Signaling I/O Termination
2.4.1. Single-Ended I/O Termination in Intel® Agilex™ Devices x
2.4.1.1. Single-Ended I/O Standard OCT Termination 2.4.1.2. OCT Calibration Block 2.4.1.3. Single-Ended I/O Standards External Termination 2.4.1.4. Single-Ended I/O Termination Implementation Guide
2.4.1.1. Single-Ended I/O Standard OCT Termination x
2.4.1.1.1. RS OCT 2.4.1.1.2. RT OCT 2.4.1.1.3. Dynamic OCT
2.4.1.4. Single-Ended I/O Termination Implementation Guide x
2.4.1.4.1. Configuring OCT Using the Assignment Editor 2.4.1.4.2. OCT Features Assignment Names and Settings
2.4.2. True Differential Signaling I/O Termination x
2.4.2.1. True Differential Signaling I/O Standard OCT Termination 2.4.2.2. True Differential Signaling I/O Standard External Termination
2.4.2.1. True Differential Signaling I/O Standard OCT Termination x
2.4.2.1.1. Configuring Differential Input RD OCT Using the Assignment Editor 2.4.2.1.2. Guidelines: Differential Input RD OCT
2.5. Intel® Agilex™ GPIO Design Guidelines x
2.5.1. VREF Sources and VREF Pins 2.5.2. I/O Standards Implementation Based on VCCIO_PIO Voltages 2.5.3. OCT Calibration Block Requirement 2.5.4. I/O Pins Placement Requirements 2.5.5. I/O Standard Selection and I/O Bank Supply Compatibility Check 2.5.6. Simultaneous Switching Noise 2.5.7. Special Pins Requirement 2.5.8. External Memory Interface Pin Placement Requirements 2.5.9. HPS Shared I/O Requirements 2.5.10. Clocking Requirements 2.5.11. SDM Shared I/O Requirements 2.5.12. Unused Pins 2.5.13. Voltage Setting for Unused GPIO Banks 2.5.14. GPIO Pins During Power Sequencing 2.5.15. Drive Strength Requirement for GPIO Input Pins 2.5.16. Maximum DC Current Restrictions 2.5.17. 1.2 V I/O Interface Voltage Level Compatibility 2.5.18. GPIO Pins for the Avalon® Streaming Interface Configuration Scheme 2.5.19. Maximum True Differential Signaling Receiver Pairs Per I/O Lane
2.6. I/O Simulation x
2.6.1. IBIS Models 2.6.2. HSPICE* Models 2.6.3. Net Length Reports
3. Intel® Agilex™ HPS I/O Banks x
3.1. HPS I/O Bank Overview 3.2. HPS I/O Features 3.3. HPS I/O Implementation Guide 3.4. Intel® Agilex™ HPS I/O Design Guidelines 3.5. HPS I/O Simulation
3.2. HPS I/O Features x
3.2.1. Supported I/O Standards for HPS I/O Banks 3.2.2. HPS I/O Buffer Behavior 3.2.3. Programmable I/O Element Features for the HPS I/O Bank
3.3. HPS I/O Implementation Guide x
3.3.1. Configuring Open Drain Feature for the HPS I/O 3.3.2. I/O Assignments with the Intel® Quartus® Prime Assignment Editor 3.3.3. Assigning Pin I/O Standards in the Intel® Quartus® Prime Pin Planner
3.3.2. I/O Assignments with the Intel® Quartus® Prime Assignment Editor x
3.3.2.1. Assigning Programmable IOE Features in the Intel® Quartus® Prime Assignment Editor 3.3.2.2. HPS I/O Programmable IOE Features Assignment Names and Settings
3.4. Intel® Agilex™ HPS I/O Design Guidelines x
3.4.1. Unused Pins 3.4.2. HPS I/O Pins During Power Sequencing 3.4.3. HPS Shared I/O Requirements
3.5. HPS I/O Simulation x
3.5.1. HPS IBIS Models 3.5.2. Net Length Reports
4. Intel® Agilex™ SDM I/O Banks x
4.1. SDM I/O Bank Overview 4.2. SDM I/O Features 4.3. Intel® Agilex™ SDM I/O Design Guidelines 4.4. SDM I/O Simulation
4.2. SDM I/O Features x
4.2.1. Supported I/O Standards for SDM I/O Banks 4.2.2. SDM I/O Buffer Behavior 4.2.3. I/O Standards and Features for Intel® Agilex™ Configuration Pins
4.3. Intel® Agilex™ SDM I/O Design Guidelines x
4.3.1. Unused Pins 4.3.2. SDM I/O Pins During Power Sequencing
4.4. SDM I/O Simulation x
4.4.1. SDM IBIS Models 4.4.2. Net Length Reports
6. Intel® Agilex™ General-Purpose I/O IPs x
6.1. GPIO Intel® FPGA IP 6.2. OCT Intel® FPGA IP
6.1. GPIO Intel® FPGA IP x
6.1.1. Release Information for GPIO Intel® FPGA IP 6.1.2. Generating the GPIO Intel® FPGA IP 6.1.3. GPIO Intel® FPGA IP Parameter Settings 6.1.4. GPIO Intel® FPGA IP Interface Signals 6.1.5. GPIO Intel® FPGA IP Architecture 6.1.6. Verifying Resource Utilization and Design Performance 6.1.7. GPIO Intel® FPGA IP Timing 6.1.8. GPIO Intel® FPGA IP Design Examples
6.1.2. Generating the GPIO Intel® FPGA IP x
6.1.2.1. Intel® FPGA IP Generation Output
6.1.3. GPIO Intel® FPGA IP Parameter Settings x
6.1.3.1. Guideline: Swap datain_h and datain_l Ports in Migrated IP
6.1.4. GPIO Intel® FPGA IP Interface Signals x
6.1.4.1. Shared Signals 6.1.4.2. Data Bit-Order for Data Interface 6.1.4.3. Input and Output Bus High and Low Bits 6.1.4.4. Data Interface Signals and Corresponding Clocks
6.1.5. GPIO Intel® FPGA IP Architecture x
6.1.5.1. GPIO Intel® FPGA IP Data Paths 6.1.5.2. Register Packing
6.1.5.1. GPIO Intel® FPGA IP Data Paths x
6.1.5.1.1. Input Path 6.1.5.1.2. Output and Output Enable Paths
6.1.7. GPIO Intel® FPGA IP Timing x
6.1.7.1. Timing Components 6.1.7.2. Delay Elements 6.1.7.3. Timing Analysis 6.1.7.4. Timing Closure Guidelines
6.1.7.3. Timing Analysis x
6.1.7.3.1. Single Data Rate Input Register 6.1.7.3.2. Full-Rate or Half-Rate DDIO Input Register 6.1.7.3.3. Single Data Rate Output Register 6.1.7.3.4. Full-Rate or Half-Rate DDIO Output Register
6.1.8. GPIO Intel® FPGA IP Design Examples x
6.1.8.1. GPIO Intel® FPGA IP Synthesizable Intel® Quartus® Prime Design Example 6.1.8.2. GPIO Intel® FPGA IP Simulation Design Example
6.2. OCT Intel® FPGA IP x
6.2.1. Release Information 6.2.2. Generating the OCT Intel® FPGA IP 6.2.3. OCT Intel® FPGA IP Parameter Settings 6.2.4. OCT Intel® FPGA IP Signals 6.2.5. QSF Assignments 6.2.6. OCT Intel® FPGA IP Architecture 6.2.7. OCT Intel® FPGA IP Design Example
6.2.2. Generating the OCT Intel® FPGA IP x
6.2.2.1. Intel® FPGA IP Generation Output
6.2.7. OCT Intel® FPGA IP Design Example x
6.2.7.1. Generating the Intel® Quartus® Prime Design Example
7. Programmable I/O Features Description x
7.1. Programmable Pre-Emphasis 7.2. Programmable De-Emphasis 7.3. Programmable Differential Output Voltage
1. Intel Agilex General-Purpose I/O Overview
2. Intel® Agilex™ F-Series and I-Series General-Purpose I/O Banks
3. Intel® Agilex™ HPS I/O Banks
4. Intel® Agilex™ SDM I/O Banks
5. Intel® Agilex™ I/O Troubleshooting Guidelines
6. Intel® Agilex™ General-Purpose I/O IPs
7. Programmable I/O Features Description
8. Documentation Related to the Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide
9. Document Revision History for the Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

9. Document Revision History for the Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.09.29 22.3
  • In the table listing the selectable I/O standards for RS OCT for GPIO banks, removed the RS OCT with calibration values for the 1.2 V LVCMOS I/O standard.
  • In the guideline for VREF sources and VREF pins, clarified that the internal VREF is supported only for external memory interfaces.
2022.06.14 22.1 Removed package R3184A.
2022.03.28 22.1
  • Restructured and rewritten the document to improve ease of reference and modularity.
  • Retitled the document from Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide to Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide.
  • Moved the LVDS SERDES sections to a new document: Intel® Agilex™ F-Series and I-Series LVDS SERDES User Guide.
  • Updated the vertical migration support figure:
    • Added Intel® Agilex™ AGI 035 and AGI 040 product lines
    • Changed packages F2581A to R2581A and R1935A to R1805A
  • Updated the slew rate control settings for the SSTL-12 I/O standard in the topic listing the programmable I/O element features for the GPIO bank.
  • Removed "Programmable open-drain output" from the list of Assignment Editor features. You can turn on the open drain feature through the GPIO Intel® FPGA IP parameter editor.
  • Added topics about IBIS models.
  • In the topic about VREF sources and VREF pins, clarified that you cannot mix the POD12 I/O standard with other voltage-referenced I/O standards in the same I/O lane.
  • Corrected the output clock name in the topic about the single data rate output register from sdr_out_clk to sdr_out_outclk.
  • Updated the figure showing the examples of True Differential Signaling receiver pairs placement to improve clarity.
  • Updated the supported slew rate values in the topic listing the HPS I/O programmable IOE features assignment names and settings.
  • Removed the user guide archives section. For the latest and previous versions of this user guide, refer to the Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide.
2021.10.29 21.3
  • Updated the topic about the I/O buffer behavior to add more details on the power up, power down, and turned off conditions.
  • Updated the guidelines for I/O pins in GPIO, HPS, and SDM banks during power sequencing.
  • Added a section listing the I/O standards and features for configuration pins in different configuration schemes.
  • Removed the table listing the configuration pin I/O standards and features.
2021.10.04 21.3
  • Updated the package selection and I/O vertical migration information.
  • Updated the topic about programmable de-emphasis:
    • The de-emphasis effect now affects signals at 1 UI or 0.5 UI depending on the interface clock frequency.
    • Restructured the content for easier reference.
  • Updated the GPIO IP version to 21.0.0.
  • Removed NCSim support.
2021.07.15 21.2 Updated the diagram that shows the simplified view of the single-ended GPIO input path to update dout[0] to dout[3] and dout[3] to dout[0].
2021.04.05 21.1
  • Updated the vertical migration table:
    • Removed the AGF 004 product line.
    • Removed the F1149A, R1615A, R2013A, R2470A, R3179C, R2581A, R3179B, and R3179A packages.
    • Added R1546A, R2340A, R3184C, F2581A, R3184B, and R3184A packages.
  • Removed H-Tile and 3 V I/O support.
  • Removed the Intel® Agilex™ AGF 014 FPGA.
  • Updated default settings for the POD-12 and Differential POD-12 I/O standards from "High" to "Off".
  • Added a topic about the Schmitt Trigger input buffer feature.
  • Added assignment settings for the Schmitt Trigger input buffer.
  • Added support for assigning 0 V, 1.2 V, or 1.5 V to the VCCIO_PIO pin in unused I/O banks.
  • Updated the figures showing the I/O bank structure to improve clarity and to remove 3 V I/O.
  • Updated the IP version for the GPIO and LVDS SERDES IPs to 20.0.0.
2020.09.28 20.3
  • Added 3 V H-Tile I/O information in the following topics:
    • General-purpose I/O and LVDS SERDES Overview.
    • Intel® Agilex™ I/O and Differential I/O Buffers.
    • I/O Banks.
    • Supported I/O Standards.
    • Programmable I/O Element (IOE) Features in Intel® Agilex™ Devices.
    • Single-Ended I/O Standard OCT Termination.
    • RS OCT.
    • Single-ended I/O Standards External Termination.
    • Input Path.
    • GPIO Intel FPGA IP Architecture.
  • Updated the voltage level of a pin signal during power down in the I/O Buffer Behavior.
  • Updated the Supported Usage Modes with Number of IP Instances in an I/O Sub-bank table to clarified the maximum number of transmitter and receiver channels per IP instance.
  • Updated lvds_clk and ext_lvds_clk signals width in the following tables:
    • Example: Generating Output Clocks Using an IOPLL IP (Receiver in Non-DPA Mode).
    • Example: Generating Output Clocks Using an IOPLL IP (Receiver in DPA or Soft-CDR Mode).
    • Example: Generating Output Clocks Using a Shared IOPLL IP for Transmitter and Receiver Channels (Receiver in DPA or Soft-CDR Mode).
  • Removed information about transmitter spanning across multiple I/O banks feature in the following topics:
    • IOPLL Parameter Values for External PLL Mode.
    • Intel® Agilex™ LVDS Interface with External PLL Mode.
  • Updated the IOPLL IP settings in the Signal Interface between IOPLL and LVDS SERDES IPs table.
  • Updated the Soft-CDR LVDS Receiver Interface with the IOPLL IP (with LVDS transmitter in the same sub-bank) figure.
  • Added the following guideline topics in the I/O Design Guidelines chapter:
    • Voltage Setting for Unused I/O Banks.
    • Drive Strength Requirement for GPIO Input Pins.
    • Observe Device Absolute Maximum Rating for 3.0 V Interfacing.
    • Use Only One Voltage for All 3 V I/O Banks.
    • Maximum True Differential Signaling RX Pairs Per I/O Lane.
    • Do Not Drive 3 V I/O Pins During Power Sequencing.
  • Updated LVDS SERDES Intel FPGA IP version to 19.5.0 with the following change:
    • Improved the power usage of the IP.
    • Removed the Duplex Feature parameter in the General Settings Tab table.
    • Updated the condition for FPGA/PLL speed grade in the PLL Settings Tab table.
  • Added short descriptions for General-purpose I/O Debug Guidelines and High-speed SERDES I/O Debug Guidelines tables.
2020.06.22 20.2
  • Changed R2560A name to R2581A in the Migration Capability Across Intel® Agilex™ Product Lines—Preliminary image.
  • Clarified that programmable de-emphasis feature is only available when using Fast slew rate setting in the Programmable IOE Feature Settings for Intel® Agilex™ GPIO Bank table and Programmable De-Emphasis section.
  • Added new GPIO Pins for Avalon-ST Configuration Scheme guideline topic.
  • Added the Troubleshooting Guidelines topic.
  • Added the following KDB links to the Transmitter Channel-to-Channel Skew and Receiver Skew Margin topics:
    • Why does the “TCCS Report” in LVDS SERDES Intel® FPGA IP SDC report an invalid TCCS value?
    • Why does the “TCCS Report” in LVDS SERDES Intel® FPGA IP SDC report an invalid TCCS value?
  • Added the release notes links to the GPIO Intel FPGA IP Release Information, OCT Intel FPGA IP Release Information, and LVDS SERDES Intel FPGA IP Release Information topics.
2020.04.13 20.1
  • Updated the Programmable IOE Feature Settings for Intel® Agilex™ GPIO Bank table with default slew rate settings for GPIO and EMIF implementations.
  • Updated the Programmable Output Slew Rate Control topic to specify different slew rate settings per design implementation.
  • Removed recommendation to use HSPICE simulation to verify output voltages in th e Programmable Open-Drain Output topic.
  • Updated guidelines in the External I/O Termination topic.
  • Added the AC-Coupled External Termination for 1.2 V VCCIO_PIO figure in the External I/O Termination.
  • Added the Simulation Models Descriptions table in the I/O Simulation topic.
  • Updated OCT Intel FPGA IP and GPIO Intel FPGA IP connections for user mode calibration in the User Mode OCT topic.
  • Added RZQ_GROUP QSF assignment description in the QSF Assignments table.
  • Added OCT block and primitive I/O buffer connection figure in the QSF Assignments topic.
  • Renamed the Guidelines for GPIO Pins During Power Sequencing section to Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing and updated the guidelines for GPIO, HPS, and SDM I/O pins in the section.
  • Updated information about LVDS SERDES Intel FPGA IP version 19.4.0:
    • Updated pll_areset signal connections in Non-DPA or DPA LVDS Receiver Interface with the IP (with LVDS transmitter in the same sub-bank), Soft-CDR LVDS Receiver Interface with the IP (with LVDS transmitter in the same sub-bank), and LVDS Transmitter Interface with the IP figures.
    • Added description for ext_pll_locked signal in the External PLL Signals for LVDS SERDES IP and the Signal Interface between IOPLL and LVDS SERDES IPs tables.
    • Added a note about the delay between the ext_pll_locked signal and the pll_locked signal assertions in the Initializing the LVDS SERDES IP in DPA Mode and the Initializing the LVDS SERDES IP in Non-DPA Mode topics.
2019.12.16 19.4
  • Updated information for GPIO Intel FPGA IP version 19.3.0:
    • Changed seriesterminationcontrol and parallelterminationcontrol signals to terminationcontrol signal.
  • Updated description on calibration block for mix I/O standards in the OCT Calibration Block topic.
  • Added information about LVDS SERDES Intel FPGA IP version 19.3.0.
  • Added Example of x4 DQ Groups with Shared OE, Reset, and Clock Enable Signals in Pinout Files figure in the Placement Requirements topic.
  • Added Simultaneous Switching Noise and Clocking Requirements topics in the I/O Design Guidelines chapter.
  • Added Placing LVDS Transmitters and Receivers in the Same I/O Bank and Using an External PLL topics in the LVDS SERDES Design Guidelines chapter.
  • Added information to generate design example for OCT Intel FPGA IP version 19.3.0.
  • Added Net Length Reports topic.
2019.09.30 19.3
  • Changed differential signaling naming from 1.5 V True Differential Signaling to True Differential Signaling.
  • Added Input and Output columns for VCCIO_PIO voltage in the Intel® Agilex™ GPIO Bank Supported I/O Standards table.
  • Added Intel® Quartus® Prime assignment names for each I/O standards.
  • Added the following topics:
    • I/O Buffer and Registers in Intel® Agilex™ Devices
    • Configuring I/O Assignments in Intel® Quartus® Prime Software
    • Configuring I/O Assignments Using Assignment Editor
    • Configuring I/O Standards Using Pin Planner
    • Configuring OCT Using Assignment Editor
    • Configuring Differential Input RD OCT Using Assignment Editor
  • Restructured the Intel® Agilex™ I/O Termination chapter.
  • Updated default RS OCT calibration values in the Selectable I/O Standards for RS OCT table.
  • Added explanation on the number of RS and RT OCT settings can a OCT calibration block supports for all I/O standards in OCT Calibration Block topic.
  • Restructured the I/O and LVDS SERDES Design Guidelines chapter.
  • Added the following diagrams in the Programmable De-Emphasis section:
    • Signal Attenuation for De-emphasis Off for SSTL and HSTL I/O Standards
    • Signal Attenuation for Constant Impedance De-emphasis for SSTL and HSTL I/O Standards
    • Signal Attenuation for Low Power De-emphasis for SSTL and HSTL I/O Standards
    • Signal Attenuation for De-emphasis Off for POD12 I/O Standard
    • Signal Attenuation for Low Power De-emphasis for POD12 I/O Standard
  • Removed maximum DC current restrictions for Intel® Agilex™ devices in the Maximum DC Current Restrictions topic.
  • Added the OCT Calibration Block Requirement topic in Intel® Agilex™ I/O Design Guidelines.
  • Added new restrictions about using AVSTx16 or AVSTx32 configuration scheme in SDM Shared I/O Requirements topic.
  • Changed maximum VREF pin leakage current from 4 µA to 8 µA.
  • Added information about GPIO Intel FPGA IP version 19.3.0.
  • Added information about OCT Intel FPGA IP version 19.3.0.
2019.04.02 19.1 Initial release.
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