Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

ID 683780
Date 9/29/2022
Public

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6.1.5.2. Register Packing

The GPIO IP allows you to pack registers into the periphery to save area and resource utilization.

You can configure the full-rate DDIO on the input and output path as a flip flop by adding .qsf assignments.

Table 51.  Register Packing .qsf Assignments
Path .qsf Assignment
Input register packing set_instance_assignment -name FAST_INPUT_REGISTER ON -to <path to register>
Output register packing set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to <path to register>
Output enable register packing set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to <path to register>
Note: The .qsf assignments do not guarantee register packing. However, these assignments enable the Fitter to find a legal placement. Otherwise, the Fitter keeps the flip flop in the core.