Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

ID 683780
Date 9/29/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.1. GPIO Bank Overview

Each GPIO bank contains a top sub-bank and a bottom sub-bank.
  • Top sub-bank—located at the edge of the die. The pin index numbers are 48 to 95.
  • Bottom sub-bank—located near the FPGA core. The pin index numbers are 0 to 47.

Each sub-bank contains four I/O lanes. Each I/O lane has 12 I/O pins. Consequently, there are a total of 48 single-ended I/O pins or 24 true differential I/O pairs in each sub-bank.

If you use SERDES, each I/O lane supports SERDES and dynamic phase alignment (DPA) channels for:

  • Three dedicated differential receiver input buffer pairs; and
  • Three dedicated differential transmitter output buffer pairs

If you do not use SERDES, you can configure each true differential buffer as receiver or transmitter.

  • Up to three differential receiver pairs within an I/O lane; and
  • Up to six differential transmitter pairs within an I/O lane.

Additionally, each sub-bank also contains dedicated circuitries including:

  • I/O PLL
  • Hard memory controller
  • On-chip termination (OCT) calibration blocks

The total number of GPIO banks varies across different device packages. Some GPIO banks are shared with the SDM and HPS function blocks. Refer to the device pin-out files for available I/O banks for each device package.