Intel® Agilex™ F-Series and I-Series General-Purpose I/O User Guide

ID 683780
Date 9/29/2022
Public
Document Table of Contents

2.5.19. Maximum True Differential Signaling Receiver Pairs Per I/O Lane

If you do not use SERDES, you can configure any of the true differential I/O buffers to a maximum of three true differential signaling receiver pairs per each I/O lane.

You can place the true differential signaling receiver pairs anywhere within the same I/O lane.

Figure 23. Examples of True Differential Signaling Receiver Pairs PlacementThis figure shows examples of three true differential signaling receiver pairs placement within an I/O lane.

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