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1. Intel® MAX® 10 I/O Overview
2. Intel® MAX® 10 I/O Architecture and Features
3. Intel® MAX® 10 I/O Design Considerations
4. Intel® MAX® 10 I/O Implementation Guides
5. GPIO Lite Intel® FPGA IP References
6. Intel® MAX® 10 General Purpose I/O User Guide Archives
7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
2.3.2.1. Programmable Open Drain
2.3.2.2. Programmable Bus Hold
2.3.2.3. Programmable Pull-Up Resistor
2.3.2.4. Programmable Current Strength
2.3.2.5. Programmable Output Slew Rate Control
2.3.2.6. Programmable IOE Delay
2.3.2.7. PCI Clamp Diode
2.3.2.8. Programmable Pre-Emphasis
2.3.2.9. Programmable Differential Output Voltage
2.3.2.10. Programmable Emulated Differential Output
2.3.2.11. Programmable Dynamic Power Down
3.1. Guidelines: VCCIO Range Considerations
3.2. Guidelines: Voltage-Referenced I/O Standards Restriction
3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers
3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules
3.5. Guidelines: I/O Restriction Rules
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin
3.7. Guidelines: Analog-to-Digital Converter I/O Restriction
3.8. Guidelines: External Memory Interface I/O Restrictions
3.9. Guidelines: Dual-Purpose Configuration Pin
3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
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2.3.2.6. Programmable IOE Delay
You can activate the programmable IOE delays to ensure zero hold times, minimize setup times, increase clock-to-output times, or delay the clock input signal. This feature helps read and write timing margins because it minimizes the uncertainties between signals in the bus.
Each pin can have a different delay value to ensure signals within a bus have the same delay going into or out of the device.
| Programmable Delays | Intel® Quartus® Prime Logic Option |
|---|---|
| Input pin-to-logic array delay | Input delay from pin to internal cells |
| Input pin-to-input register delay | Input delay from pin to input register |
| Output pin delay | Delay from output register to output pin |
| Dual-purpose clock input pin delay | Input delay from dual-purpose clock pin to fan-out destinations |
There are two paths in the IOE for an input to reach the logic array. Each of the two paths can have a different delay. This allows you to adjust delays from the pin to the internal logic element (LE) registers that reside in two different areas of the device. You must set the two combinational input delays with the input delay from pin to internal cells logic option in the Intel® Quartus® Prime software for each path. If the pin uses the input register, one of the delays is disregarded and the delay is set with the input delay from pin to input register logic option in the Intel® Quartus® Prime software.
The IOE registers in each I/O block share the same source for the preset or clear features. You can program preset or clear for each individual IOE, but you cannot use both features simultaneously. You can also program the registers to power-up high or low after configuration is complete. If programmed to power-up low, an asynchronous clear can control the registers. If programmed to power-up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of the active-low input of another device upon power up. If one register in an IOE uses a preset or clear signal, all registers in the IOE must use that same signal if they require preset or clear. Additionally, a synchronous reset signal is available for the IOE registers.