Intel® MAX® 10 General Purpose I/O User Guide

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ID 683751
Date 1/27/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 I/O Overview 2. Intel® MAX® 10 I/O Architecture and Features 3. Intel® MAX® 10 I/O Design Considerations 4. Intel® MAX® 10 I/O Implementation Guides 5. GPIO Lite Intel® FPGA IP References 6. Intel® MAX® 10 General Purpose I/O User Guide Archives 7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
1. Intel® MAX® 10 I/O Overview x
1.1. Intel® MAX® 10 Devices I/O Resources Per Package 1.2. Intel® MAX® 10 I/O Vertical Migration Support
2. Intel® MAX® 10 I/O Architecture and Features x
2.1. Intel® MAX® 10 I/O Standards Support 2.2. Intel® MAX® 10 I/O Elements 2.3. Intel® MAX® 10 I/O Buffers 2.4. I/O Standards Termination
2.1. Intel® MAX® 10 I/O Standards Support x
2.1.1. Intel® MAX® 10 I/O Standards Voltage and Pin Support
2.2. Intel® MAX® 10 I/O Elements x
2.2.1. Intel® MAX® 10 I/O Banks Architecture 2.2.2. Intel® MAX® 10 I/O Banks Performance 2.2.3. Intel® MAX® 10 I/O Banks Locations
2.3. Intel® MAX® 10 I/O Buffers x
2.3.1. Schmitt-Trigger Input Buffer 2.3.2. Programmable I/O Buffer Features
2.3.2. Programmable I/O Buffer Features x
2.3.2.1. Programmable Open Drain 2.3.2.2. Programmable Bus Hold 2.3.2.3. Programmable Pull-Up Resistor 2.3.2.4. Programmable Current Strength 2.3.2.5. Programmable Output Slew Rate Control 2.3.2.6. Programmable IOE Delay 2.3.2.7. PCI Clamp Diode 2.3.2.8. Programmable Pre-Emphasis 2.3.2.9. Programmable Differential Output Voltage 2.3.2.10. Programmable Emulated Differential Output 2.3.2.11. Programmable Dynamic Power Down
2.4. I/O Standards Termination x
2.4.1. Voltage-Referenced I/O Standards Termination 2.4.2. Differential I/O Standards Termination 2.4.3. Intel® MAX® 10 On-Chip I/O Termination
2.4.3. Intel® MAX® 10 On-Chip I/O Termination x
2.4.3.1. OCT Calibration 2.4.3.2. RS OCT in Intel® MAX® 10 Devices
3. Intel® MAX® 10 I/O Design Considerations x
3.1. Guidelines: VCCIO Range Considerations 3.2. Guidelines: Voltage-Referenced I/O Standards Restriction 3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules 3.5. Guidelines: I/O Restriction Rules 3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin 3.7. Guidelines: Analog-to-Digital Converter I/O Restriction 3.8. Guidelines: External Memory Interface I/O Restrictions 3.9. Guidelines: Dual-Purpose Configuration Pin 3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin x
3.6.1. Calculating the Total Inductance for 1.0 V Pin Placement
4. Intel® MAX® 10 I/O Implementation Guides x
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP 4.2. Verifying Pin Migration Compatibility
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP x
4.1.1. GPIO Lite Intel® FPGA IP Data Paths
4.1.1. GPIO Lite Intel® FPGA IP Data Paths x
4.1.1.1. DDR Input Path 4.1.1.2. DDR Output Path with Output Enable
5. GPIO Lite Intel® FPGA IP References x
5.1. GPIO Lite Intel® FPGA IP Parameter Settings 5.2. GPIO Lite Intel® FPGA IP Interface Signals
1. Intel® MAX® 10 I/O Overview
2. Intel® MAX® 10 I/O Architecture and Features
3. Intel® MAX® 10 I/O Design Considerations
4. Intel® MAX® 10 I/O Implementation Guides
5. GPIO Lite Intel® FPGA IP References
6. Intel® MAX® 10 General Purpose I/O User Guide Archives
7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide

2.1.1. Intel® MAX® 10 I/O Standards Voltage and Pin Support

Table 4.   Intel® MAX® 10 I/O Standards Voltage Levels and Pin Support
Note: The I/O standards that each pin type supports depends on the I/O standards that the pin's I/O bank supports. For example, only the bottom I/O banks support the LVDS (dedicated) I/O standard. You can use the LVDS (dedicated) I/O standard for the PLL_CLKOUT pin only if the pin is available in your device's bottom I/O banks. To determine the pin's I/O bank locations for your device, check your device's pin out file.
I/O Standard VCCIO (V) VREF (V) Pin Type Support
Input Output PLL_CLKOUT MEM_CLK CLK DQS User I/O
3.3 V LVTTL/3.3 V LVCMOS 3.3/3.0/2.5 3.3 — Yes Yes Yes Yes Yes
3.0 V LVTTL/3.0 V LVCMOS 3.0/2.5 3.0 — Yes Yes Yes Yes Yes
2.5 V LVCMOS 3.0/2.5 2.5 — Yes Yes Yes Yes Yes
1.8 V LVCMOS 1.8/1.5 1.8 — Yes Yes Yes Yes Yes
1.5 V LVCMOS 1.8/1.5 1.5 — Yes Yes Yes Yes Yes
1.2 V LVCMOS 1.2 1.2 — Yes Yes Yes Yes Yes
1.0 V LVCMOS 1.0 9 1.09 — — — Yes — Yes
3.0 V PCI 3.0 3.0 — Yes Yes Yes Yes Yes
3.3 V Schmitt Trigger 3.3 — — — — Yes Yes 10 Yes
2.5 V Schmitt Trigger 2.5 — — — — Yes Yes10 Yes
1.8 V Schmitt Trigger 1.8 — — — — Yes Yes10 Yes
1.5 V Schmitt Trigger 1.5 — — — — Yes Yes10 Yes
SSTL-2 Class I 2.5 2.5 1.25 Yes Yes Yes Yes Yes
SSTL-2 Class II 2.5 2.5 1.25 Yes Yes Yes Yes Yes
SSTL-18 Class I 1.8 1.8 0.9 Yes Yes Yes Yes Yes
SSTL-18 Class II 1.8 1.8 0.9 Yes Yes Yes Yes Yes
SSTL-15 Class I 1.5 1.5 0.75 Yes Yes Yes Yes Yes
SSTL-15 Class II 1.5 1.5 0.75 Yes Yes Yes Yes Yes
SSTL-15 1.5 1.5 0.75 Yes Yes Yes Yes Yes
SSTL-135 1.35 1.35 0.675 Yes Yes Yes Yes Yes
1.8 V HSTL Class I 1.8 1.8 0.9 Yes Yes Yes Yes Yes
1.8 V HSTL Class II 1.8 1.8 0.9 Yes Yes Yes Yes Yes
1.5 V HSTL Class I 1.5 1.5 0.75 Yes Yes Yes Yes Yes
1.5 V HSTL Class II 1.5 1.5 0.75 Yes Yes Yes Yes Yes
1.2 V HSTL Class I 1.2 1.2 0.6 Yes Yes Yes Yes Yes
1.2 V HSTL Class II 1.2 1.2 0.6 Yes Yes Yes Yes Yes
HSUL-12 1.2 1.2 0.6 Yes Yes Yes Yes Yes
Differential SSTL-2 Class I and II — 2.5 — Yes Yes — Yes —
2.5 — 1.25 — — Yes Yes —
Differential SSTL-18 Class I and Class II — 1.8 — Yes Yes — Yes —
1.8 — 0.9 — — Yes Yes —
Differential SSTL-15 Class I and Class II — 1.5 — Yes Yes — Yes —
1.5 — 0.75 — — Yes Yes —
Differential SSTL-15 — 1.5 — Yes Yes — Yes —
1.5 — 0.75 — — Yes Yes —
Differential SSTL-135 — 1.35 — Yes Yes — Yes —
1.35 — 0.675 — — Yes Yes —
Differential 1.8 V HSTL Class I and Class II — 1.8 — Yes Yes — Yes —
1.8 — 0.9 — — Yes Yes —
Differential 1.5 V HSTL Class I and Class II — 1.5 — Yes Yes — Yes —
1.5 — 0.75 — — Yes Yes —
Differential 1.2 V HSTL Class I and Class II — 1.2 — Yes Yes — Yes —
1.2 — 0.6 — — Yes Yes —
Differential HSUL-12 — 1.2 — Yes Yes — Yes —
1.2 — 0.6 — — Yes Yes —
LVDS (dedicated) 2.5 2.5 — Yes Yes Yes — Yes
LVDS (emulated, external resistors) — 2.5 — Yes Yes — — Yes
Mini-LVDS (dedicated) — 2.5 — Yes Yes — — Yes
Mini-LVDS (emulated, external resistor) — 2.5 — Yes Yes — — Yes
RSDS (dedicated) — 2.5 — Yes Yes — — Yes
RSDS (emulated, external resistor, 1R) — 2.5 — Yes Yes — — Yes
RSDS (emulated, external resistors, 3R) — 2.5 — Yes Yes — — Yes
PPDS (dedicated) — 2.5 — Yes Yes — — Yes
PPDS (emulated, external resistor) — 2.5 — Yes Yes — — Yes
LVPECL 2.5 — — — — Yes — —
Bus LVDS 2.5 2.5 — — — — — Yes
TMDS 2.5 — — — — Yes — Yes
Sub-LVDS 2.5 1.8 — Yes Yes Yes — Yes
SLVS 2.5 2.5 — Yes Yes Yes — Yes
HiSpi 2.5 — — — — Yes — Yes
Related Information
9 Not supported on bank 1B and bank 8.
10 Bidirectional—use Schmitt Trigger input with LVTTL output.
Level Two Title