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1. Intel® MAX® 10 I/O Overview 2. Intel® MAX® 10 I/O Architecture and Features 3. Intel® MAX® 10 I/O Design Considerations 4. Intel® MAX® 10 I/O Implementation Guides 5. GPIO Lite Intel® FPGA IP References 6. Intel® MAX® 10 General Purpose I/O User Guide Archives 7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
18.104.22.168. Programmable Open Drain 22.214.171.124. Programmable Bus Hold 126.96.36.199. Programmable Pull-Up Resistor 188.8.131.52. Programmable Current Strength 184.108.40.206. Programmable Output Slew Rate Control 220.127.116.11. Programmable IOE Delay 18.104.22.168. PCI Clamp Diode 22.214.171.124. Programmable Pre-Emphasis 126.96.36.199. Programmable Differential Output Voltage 188.8.131.52. Programmable Emulated Differential Output 184.108.40.206. Programmable Dynamic Power Down
3.1. Guidelines: VCCIO Range Considerations 3.2. Guidelines: Voltage-Referenced I/O Standards Restriction 3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules 3.5. Guidelines: I/O Restriction Rules 3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin 3.7. Guidelines: Analog-to-Digital Converter I/O Restriction 3.8. Guidelines: External Memory Interface I/O Restrictions 3.9. Guidelines: Dual-Purpose Configuration Pin 3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
3.1. Guidelines: VCCIO Range Considerations
There are several VCCIO range considerations because of I/O pin configuration function and I/O bank location.
- Banks 1 and 8 have I/O pins with configuration function. The configuration function of these pins support only 1.5 V to 3.3 V. If you want to access the configuration function of these pins during user mode (run time), for example JTAG pins, the VCCIO of the pin's bank is limited to a range of 1.5 V to 3.3 V. If you want to use I/O standards with 1.2 V to 1.35 V in bank 1 or 8 during user mode, do not use the configuration function of the bank's I/O pins.
- For devices with banks 1A and 1B:
- If you use the VREF pin or the ADC, you must supply a common VCCIO voltage to banks 1A and 1B.
- If you do not use the VREF pin or the ADC, you can supply separate VCCIO voltages to banks 1A and 1B.
- If you plan to migrate from devices that has banks 1A and 1B to devices that has only bank 1, ensure that the VCCIO of bank 1A and 1B are the same.
- For the V36 package of the 10M02 device, the VCCIO of these groups of I/O banks must be the same:
- Group 1—banks 1, 2 and 8
- Group 2—banks 3, 5, and 6
- For the V81 package of the 10M08 device, the VCCIO of these groups of I/O banks must be the same:
- Group 1—banks 1A, 1B, and 2
- Group 2—banks 5 and 6
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