Intel® MAX® 10 General Purpose I/O User Guide

ID 683751
Date 1/27/2022
Public

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4.1.1. GPIO Lite Intel® FPGA IP Data Paths

Table 25.   GPIO Lite IP Core Data Path Modes
Data Path Mode
Bypass Single Register DDR
Input Data goes from the delay element to the core, bypassing all double data rate I/Os (DDIOs). The full-rate DDIO operates as a single register. The full-rate DDIO operates as a regular DDIO.
Output Data goes from the core straight to the delay element, bypassing all DDIOs. The full-rate DDIO operates as a single register. The full-rate DDIO operates as a regular DDIO.
Bidirectional The output buffer drives both an output pin and an input buffer. The full-rate DDIO operates as a single register. The output buffer drives both an output pin and an input buffer. The full-rate DDIO operates as a regular DDIO. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops.

If you use asynchronous clear and preset signals, all DDIOs share these same signals.

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