Intel® MAX® 10 General Purpose I/O User Guide

ID 683751
Date 1/27/2022
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5.2. GPIO Lite Intel® FPGA IP Interface Signals

Depending on parameter settings you specify, different interface signals are available for the GPIO Lite IP core.
Table 29.  Pad Interface SignalsThe pad interface connects the GPIO Lite IP core to the pads.
Signal Name Direction Description
pad_in Input

Input pad port if you use the input path.

pad_in_b Input

Input negative pad port if you use the input path and enable the true or pseudo differential buffers.

pad_out Output

Output pad port if you use the output path.

pad_out_b Output

Output negative pad port if you use the output path and enable the true of pseudo differential buffers.

pad_io Bidirectional

Bidirectional pad port if you use bidirectional paths.

pad_io_b Bidirectional

Bidirectional negative pad port if you use bidirectional paths and enable true or pseudo differential buffers.

Table 30.  Data Interface SignalsThe data interface is an input or output interface from the GPIO Lite IP core to the FPGA core.
Signal Name Direction Description
din Input

Data received from the input pin.

Signal width for each input pin:

  • DDR mode—2
  • Other modes—1
dout Output

Data to send out through the output pin.

Signal width for each output pin:

  • DDR mode—2
  • Other modes—1
oe Input

Control signal that enables the output buffer. This signal is active HIGH.

nsleep Input

Control signal that enables the input buffer. This signal is active LOW.

This signal is available for the 10M16, 10M25, 10M40, and 10M50 devices.

Table 31.   Clock Interface SignalsThe clock interface is an input clock interface. It consists of different signals, depending on the configuration. The GPIO Lite IP core can have zero, one, two, or four clock inputs. Clock ports appear differently in different configurations to reflect the actual function performed by the clock signal.
Signal Name Direction Description
inclock Input

Input clock that clocks the registers in the input path.

inclocken Input

Control signal that controls when data is clocked in. This signal is active HIGH.

outclock Input

Input clock that clocks the registers in the output path.

ouctlocken Input

Control signal that controls when data is clocked out. This signal is active HIGH.

Table 32.  Reset Interface SignalsThe reset interface connects the GPIO Lite IP core to the DDIOs.
Signal Name Direction Description
aclr Input

Control signal for asynchronous clear that sets the register output state to 0. This signal is active HIGH.

aset Input

Control signal for asynchronous preset that sets the register output state to 1. This signal is active HIGH.

sclr Input

Control signal for synchronous clear that sets the register output to 0. This signal is active HIGH.