Intel® MAX® 10 General Purpose I/O User Guide

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ID 683751
Date 1/27/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 I/O Overview 2. Intel® MAX® 10 I/O Architecture and Features 3. Intel® MAX® 10 I/O Design Considerations 4. Intel® MAX® 10 I/O Implementation Guides 5. GPIO Lite Intel® FPGA IP References 6. Intel® MAX® 10 General Purpose I/O User Guide Archives 7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
1. Intel® MAX® 10 I/O Overview x
1.1. Intel® MAX® 10 Devices I/O Resources Per Package 1.2. Intel® MAX® 10 I/O Vertical Migration Support
2. Intel® MAX® 10 I/O Architecture and Features x
2.1. Intel® MAX® 10 I/O Standards Support 2.2. Intel® MAX® 10 I/O Elements 2.3. Intel® MAX® 10 I/O Buffers 2.4. I/O Standards Termination
2.1. Intel® MAX® 10 I/O Standards Support x
2.1.1. Intel® MAX® 10 I/O Standards Voltage and Pin Support
2.2. Intel® MAX® 10 I/O Elements x
2.2.1. Intel® MAX® 10 I/O Banks Architecture 2.2.2. Intel® MAX® 10 I/O Banks Performance 2.2.3. Intel® MAX® 10 I/O Banks Locations
2.3. Intel® MAX® 10 I/O Buffers x
2.3.1. Schmitt-Trigger Input Buffer 2.3.2. Programmable I/O Buffer Features
2.3.2. Programmable I/O Buffer Features x
2.3.2.1. Programmable Open Drain 2.3.2.2. Programmable Bus Hold 2.3.2.3. Programmable Pull-Up Resistor 2.3.2.4. Programmable Current Strength 2.3.2.5. Programmable Output Slew Rate Control 2.3.2.6. Programmable IOE Delay 2.3.2.7. PCI Clamp Diode 2.3.2.8. Programmable Pre-Emphasis 2.3.2.9. Programmable Differential Output Voltage 2.3.2.10. Programmable Emulated Differential Output 2.3.2.11. Programmable Dynamic Power Down
2.4. I/O Standards Termination x
2.4.1. Voltage-Referenced I/O Standards Termination 2.4.2. Differential I/O Standards Termination 2.4.3. Intel® MAX® 10 On-Chip I/O Termination
2.4.3. Intel® MAX® 10 On-Chip I/O Termination x
2.4.3.1. OCT Calibration 2.4.3.2. RS OCT in Intel® MAX® 10 Devices
3. Intel® MAX® 10 I/O Design Considerations x
3.1. Guidelines: VCCIO Range Considerations 3.2. Guidelines: Voltage-Referenced I/O Standards Restriction 3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules 3.5. Guidelines: I/O Restriction Rules 3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin 3.7. Guidelines: Analog-to-Digital Converter I/O Restriction 3.8. Guidelines: External Memory Interface I/O Restrictions 3.9. Guidelines: Dual-Purpose Configuration Pin 3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin x
3.6.1. Calculating the Total Inductance for 1.0 V Pin Placement
4. Intel® MAX® 10 I/O Implementation Guides x
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP 4.2. Verifying Pin Migration Compatibility
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP x
4.1.1. GPIO Lite Intel® FPGA IP Data Paths
4.1.1. GPIO Lite Intel® FPGA IP Data Paths x
4.1.1.1. DDR Input Path 4.1.1.2. DDR Output Path with Output Enable
5. GPIO Lite Intel® FPGA IP References x
5.1. GPIO Lite Intel® FPGA IP Parameter Settings 5.2. GPIO Lite Intel® FPGA IP Interface Signals
1. Intel® MAX® 10 I/O Overview
2. Intel® MAX® 10 I/O Architecture and Features
3. Intel® MAX® 10 I/O Design Considerations
4. Intel® MAX® 10 I/O Implementation Guides
5. GPIO Lite Intel® FPGA IP References
6. Intel® MAX® 10 General Purpose I/O User Guide Archives
7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide

2.1. Intel® MAX® 10 I/O Standards Support

Intel® MAX® 10 devices support a wide range of I/O standards, including single-ended, voltage-referenced single-ended, and differential I/O standards.
Table 3.  Supported I/O Standards in Intel® MAX® 10 Devices

The voltage-referenced I/O standards are not supported in the following I/O banks of these device packages:

  • All I/O banks of V36 package of 10M02.
  • All I/O banks of V81 package of 10M08.
  • Banks 1A and 1B of E144 package of 10M50.
I/O Standard Type Device Support Direction Application Standard Support
Input Output
3.3 V LVTTL/3.3 V LVCMOS Single-ended All Yes Yes General purpose JESD8-B
3.0 V LVTTL/3.0 V LVCMOS Single-ended All Yes Yes General purpose JESD8-B
2.5 V LVCMOS Single-ended All Yes Yes General purpose JESD8-5
1.8 V LVCMOS Single-ended All Yes Yes General purpose JESD8-7
1.5 V LVCMOS Single-ended All Yes Yes General purpose JESD8-11
1.2 V LVCMOS Single-ended All Yes Yes General purpose JESD8-12
1.0 V LVCMOS 1 Single-ended Specific devices1 Yes Yes General purpose —
3.0 V PCI Single-ended All Yes Yes General purpose PCI Rev. 2.2
3.3 V Schmitt Trigger Single-ended All Yes — General purpose —
2.5 V Schmitt Trigger Single-ended All Yes — General purpose —
1.8 V Schmitt Trigger Single-ended All Yes — General purpose —
1.5 V Schmitt Trigger Single-ended All Yes — General purpose —
SSTL-2 Class I Voltage-referenced All Yes Yes DDR1 JESD8-9B
SSTL-2 Class II Voltage-referenced All Yes Yes DDR1 JESD8-9B
SSTL-18 Class I Voltage-referenced All Yes Yes DDR2 JESD8-15
SSTL-18 Class II Voltage-referenced All Yes Yes DDR2 JESD8-15
SSTL-15 Class I Voltage-referenced All Yes Yes DDR3 —
SSTL-15 Class II Voltage-referenced All Yes Yes DDR3 —
SSTL-15 2 Voltage-referenced All Yes Yes DDR3 JESD79-3D
SSTL-1352 Voltage-referenced All Yes Yes DDR3L —
1.8 V HSTL Class I Voltage-referenced All Yes Yes DDR II+, QDR II+, and RLDRAM 2 JESD8-6
1.8 V HSTL Class II Voltage-referenced All Yes Yes DDR II+, QDR II+, and RLDRAM 2 JESD8-6
1.5 V HSTL Class I Voltage-referenced All Yes Yes DDR II+, QDR II+, QDR II, and RLDRAM 2 JESD8-6
1.5 V HSTL Class II Voltage-referenced All Yes Yes DDR II+, QDR II+, QDR II, and RLDRAM 2 JESD8-6
1.2 V HSTL Class I Voltage-referenced All Yes Yes General purpose JESD8-16A
1.2 V HSTL Class II Voltage-referenced All Yes Yes General purpose JESD8-16A
HSUL-122 Voltage-referenced All Yes Yes LPDDR2 —
Differential SSTL-2 Class I and II Differential All Yes 3 Yes 4 DDR1 JESD8-9B
Differential SSTL-18 Class I and Class II Differential All Yes3 Yes4 DDR2 JESD8-15
Differential SSTL-15 Class I and Class II Differential All Yes3 Yes4 DDR3 —
Differential SSTL-15 Differential All Yes3 Yes4 DDR3 JESD79-3D
Differential SSTL-135 Differential All Yes3 Yes4 DDR3L —
Differential 1.8 V HSTL Class I and Class II Differential All Yes3 Yes4 DDR II+, QDR II+, and RLDRAM 2 JESD8-6
Differential 1.5 V HSTL Class I and Class II Differential All Yes3 Yes4 DDR II+, QDR II+, QDR II, and RLDRAM 2 JESD8-6
Differential 1.2 V HSTL Class I and Class II Differential All Yes3 Yes4 General purpose JESD8-16A
Differential HSUL-12 Differential All Yes3 Yes4 LPDDR2 —
LVDS (dedicated) 5 Differential All Yes Yes — ANSI/TIA/EIA-644
LVDS (emulated, external resistors) Differential All — Yes — ANSI/TIA/EIA-644
Mini-LVDS (dedicated)5 Differential All — Yes — —
Mini-LVDS (emulated, external resistor) Differential Dual supply devices — Yes — —
RSDS (dedicated)5 Differential All — Yes — —
RSDS (emulated, external resistor, 1R) Differential Dual supply devices — Yes — —
RSDS (emulated, external resistors, 3R) Differential All — Yes — —
PPDS (dedicated)5 Differential Dual supply devices — Yes — —
PPDS (emulated, external resistor) Differential Dual supply devices — Yes — —
LVPECL Differential All Yes — — —
Bus LVDS Differential All Yes Yes6 — —
TMDS Differential Dual supply devices Yes — — —
Sub-LVDS Differential Dual supply devices Yes Yes7 — —
SLVS Differential Dual supply devices Yes Yes8 — —
HiSpi Differential Dual supply devices Yes — — —

Section Content
Intel MAX 10 I/O Standards Voltage and Pin Support

Related Information
1 The 1.0 V LVCMOS I/O standard is available only for the following device combinations and subject to device OPN availability:

10M02/04/08/16/25/40/50 + SC/DC/SA/DA/DD + U324/U169/F256/F484 + I7/C7/C8

2 Available in Intel® MAX® 10 16, 25, 40, and 50 devices only.
3 The inputs treat differential inputs as two single-ended inputs and decode only one of them.
4 The outputs use two single-ended output buffers with the second output buffer programmed as inverted.
5 You can use dedicated LVDS transmitters only on the bottom I/O banks. You can use LVDS receivers on all I/O banks.
6 The outputs use two single-ended output buffers with the second output buffer programmed as inverted. A single series resistor is required.
7 Requires external termination resistors.
8 The outputs uses two single-ended output buffers as emulated differential outputs. Requires external termination resistors.
Level Two Title