Intel® MAX® 10 General Purpose I/O User Guide

ID 683751
Date 1/27/2022

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Document Table of Contents DDR Input Path

The pad sends data to the input buffer and the input buffer feeds the delay element. From the delay element, the data is fed to the DDIO stage, which consists of three registers:

  • RegAi samples the data from pad_in at the positive clock edge.
  • RegBi samples the data from pad_in at the negative clock edge.
  • RegCi samples the data from RegAi at the negative clock edge.
Figure 15. Simplified View of GPIO Lite IP Core DDR Input Path

Figure 16.  GPIO Lite IP Core Input Path Timing Diagram

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