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1. Intel® MAX® 10 I/O Overview 2. Intel® MAX® 10 I/O Architecture and Features 3. Intel® MAX® 10 I/O Design Considerations 4. Intel® MAX® 10 I/O Implementation Guides 5. GPIO Lite Intel® FPGA IP References 6. Intel® MAX® 10 General Purpose I/O User Guide Archives 7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
18.104.22.168. Programmable Open Drain 22.214.171.124. Programmable Bus Hold 126.96.36.199. Programmable Pull-Up Resistor 188.8.131.52. Programmable Current Strength 184.108.40.206. Programmable Output Slew Rate Control 220.127.116.11. Programmable IOE Delay 18.104.22.168. PCI Clamp Diode 22.214.171.124. Programmable Pre-Emphasis 126.96.36.199. Programmable Differential Output Voltage 188.8.131.52. Programmable Emulated Differential Output 184.108.40.206. Programmable Dynamic Power Down
3.1. Guidelines: VCCIO Range Considerations 3.2. Guidelines: Voltage-Referenced I/O Standards Restriction 3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules 3.5. Guidelines: I/O Restriction Rules 3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin 3.7. Guidelines: Analog-to-Digital Converter I/O Restriction 3.8. Guidelines: External Memory Interface I/O Restrictions 3.9. Guidelines: Dual-Purpose Configuration Pin 3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
2.2.1. Intel® MAX® 10 I/O Banks Architecture
The I/O elements are located in a group of four modules per I/O bank:
- High speed DDR3 I/O banks—supports various I/O standards and protocols including DDR3. These I/O banks are available only on the right side of the device.
- High speed I/O banks—supports various I/O standards and protocols except DDR3. These I/O banks are available on the top, left, and bottom sides of the device.
- Low speed I/O banks—lower speeds I/O banks that are located at the top left side of the device.
For more information about I/O pins support, refer to the pinout files for your device.
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