Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 6/03/2020
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

2.1.4. Understanding the Files Generated

Table 8.  Overview of Qsys Generation Output Files

Directory

Description

<testbench_dir>/<variant_name>/synthesis

Includes the top‑level HDL file for the Hard IP for PCI Express and the .qip file that lists all of the necessary assignments and information required to process the IP core in the Quartus® Prime compiler. Generally, a single .qip file is generated for each IP core.

<testbench_dir>/<variant_name>/synthesis/submodules

Includes the HDL files necessary for Quartus® Prime synthesis.

<testbench_dir>/<variant_name>/testbench

Includes testbench subdirectories for the Aldec, Cadence, Synopsys, and Mentor simulation tools with the required libraries and simulation scripts.

<testbench_dir>/<variant_name>/testbench<cad_vendor>

Includes the HDL source files and scripts for the simulation testbench.

For a more detailed listing of the directories and files the Quartus® Prime software generates, refer to Files Generated for Intel IP Cores in Compiling the Design in the Qsys Design Flow.