Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 6/03/2020

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Document Table of Contents

A.1. TLP Packet Formats without Data Payload

The following figures show the header format for TLPs without a data payload.

For more information about the alignment of 3- and 4-dword headers refer to the related links below for Data Alignment and Timing for the Avalon-ST TX and RX Interfaces.

Figure 81. Memory Read Request, 32-Bit Addressing
Figure 82. Memory Read Request, Locked 32-Bit Addressing
Figure 83. Memory Read Request, 64-Bit Addressing
Figure 84. Memory Read Request, Locked 64-Bit Addressing
Figure 85. Configuration Read Request Root Port (Type 1)
Figure 86. I/O Read Request
Figure 87. Message without Data

Figure 88. Completion without Data
Figure 89. Completion Locked without Data