Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 6/03/2020
Public

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1.5. Configurations

The Arria V Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack comprising the following layers:

  • Physical (PHY), including:
    • Physical Media Attachment (PMA)
    • Physical Coding Sublayer (PCS)
  • Media Access Control (MAC)
  • Data Link Layer (DL)
  • Transaction Layer (TL)

The Hard IP supports all memory, I/O, configuration, and message transactions. It is optimized for Intel devices. The Application Layer interface is also optimized to achieve maximum effective throughput. You can customize the Hard IP to meet your design requirements.

Figure 2. PCI Express Application with a Single Root Port and EndpointThe following figure shows a PCI Express link between two Arria V FPGAs. One is configured as a Root Port and the other as an Endpoint.
Figure 3. PCI Express Application with an Endpoint Using the Multi-Function CapabilityThe following figure shows a PCI Express link between two Intel FPGAs. One is configured as a Root Port and the other as a multi-function Endpoint. The FPGA serves as a custom I/O hub for the host CPU. In the Arria V FPGA, each peripheral is treated as a function with its own set of Configuration Space registers. Eight multiplexed functions operate using a single PCI Express link.
Figure 4. PCI Express Application Using Configuration via Protocol The Arria V design below includes the following components:
  • A Root Port that connects directly to a second FPGA that includes an Endpoint.
  • Two Endpoints that connect to a PCIe switch.
  • A host CPU that implements CvP using the PCI Express link connects through the switch. For more information about configuration over a PCI Express link below.