Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 6/03/2020

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4.13.1. Transceiver Reconfiguration

Dynamic reconfiguration compensates for variations due to process, voltage and temperature (PVT). Among the analog settings that you can reconfigure are V OD, pre-emphasis, and equalization.

You can use the Altera Transceiver Reconfiguration Controller to dynamically reconfigure analog settings. For Gen2 operation, you must turn on Enable duty cycle calibration in the Transceiver Reconfiguration Controller GUI. Arria® V devices require duty cycle calibration (DCD) for data rates greater than 4.9152 Gbps. For more information about instantiating the Altera Transceiver Reconfiguration Controller IP core refer to Hard IP Reconfiguration .

Table 41.  Transceiver Control SignalsIn this table, <n> is the number of interfaces required.

Signal Name





Reconfiguration signals to the Transceiver Reconfiguration Controller.



Reconfiguration signals from the Transceiver Reconfiguration Controller.

The following table shows the number of logical reconfiguration and physical interfaces required for various configurations. The Quartus® Prime Fitter merges logical interfaces to minimize the number of physical interfaces configured in the hardware. Typically, one logical interface is required for each channel and one for each PLL.

The ×8 variants require an extra channel for PCS clock routing and control. The ×8 variants use channel 4 for clocking.

Table 42.  Number of Logical and Physical Reconfiguration Interfaces


Logical Interfaces

Gen1 and Gen2 ×1


Gen1 and Gen2 ×2


Gen1 and Gen2 ×4


Gen1 ×8


For more information about the Transceiver Reconfiguration Controller, refer to the Transceiver Reconfiguration Controller chapter in the Altera Transceiver PHY IP Core User Guide .