Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 6/03/2020
Public

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Document Table of Contents

2.1.1. Generating the Testbench

Follow these steps to generate the chaining DMA testbench:

  1. On the Generate menu, select Generate Testbench System. Specify the parameters listed in the following table.
    Table 7.  Parameters to Specify on the Generation Tab in Qsys

    Parameter

    Value

    Create testbench Qsys system

    Standard, BFMs for standard Qsys interfaces

    Create testbench simulation model

    Verilog

    Allow mixed-language simulation

    Turn this option off

    Output Directory

    Path

    <working_dir>/pcie_de_gen1_x4_ast64

    Testbench

    <working_dir>/pcie_de_gen1_x4_ast64/testbench

  2. Click the Generate button at the bottom of the Generation tab to create the testbench.