Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 6/03/2020
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4.5. Error Signals

The following table describes the ECC error signals. These signals are all valid for one clock cycle. They are synchronous to coreclkout_hip.

ECC for the RX and retry buffers is implemented with MRAM. These error signals are flags. If a specific location of MRAM has errors, as long as that data is in the ECC decoder, the flag indicates the error.

When a correctable ECC error occurs, the Arria V Hard IP for PCI Express recovers without any loss of information. No Application Layer intervention is required. In the case of uncorrectable ECC error, Intel recommends that you reset the core.

The Avalon-ST rx_st_err indicates an uncorrectable error in the RX buffer. This signal is described in 64- or 128-Bit Avalon-ST RX Datapath in the Avalon-ST RX Interface description.

Table 30.  Error Signals

Signal

I/O

Description

derr_cor_ext_rcv0

Output

Indicates a corrected error in the RX buffer. This signal is for debug only. It is not valid until the RX buffer is filled with data. This is a pulse, not a level, signal. Internally, the pulse is generated with the 500 MHz clock. A pulse extender extends the signal so that the FPGA fabric running at 250 MHz can capture it. Because the error was corrected by the IP core, no Application Layer intervention is required.  (1)

derr_rpl

Output

Indicates an uncorrectable error in the retry buffer. This signal is for debug only. (1)

derr_cor_ext_rpl0

Output

Indicates a corrected ECC error in the retry buffer. This signal is for debug only. Because the error was corrected by the IP core, no Application Layer intervention is required.  (1)

Notes:

  1. Debug signals are not rigorously verified and should only be used to observe behavior. Debug signals should not be used to drive logic custom logic.