Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 6/03/2020

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Document Table of Contents

1.1. Arria V Avalon-ST Interface for PCIe Datasheet

Altera® Arria® V FPGAs include a configurable, hardened protocol stack for PCI Express® that is compliant with PCI Express Base Specification 2.1 or 3.0. The Hard IP for PCI Express using the Avalon Streaming (Avalon-ST) interface is the most flexible variant. However, this variant requires a thorough understanding of the PCIe® Protocol. The following figure shows the high-level modules and connecting interfaces for this variant.

Figure 1.  Arria V PCIe Variant with Avalon-ST Interface
Table 1.  PCI Express Data Throughput

The following table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead.

Link Width
×1 ×2 ×4 ×8

PCI Express Gen1 (2.5 Gbps)





PCI Express Gen2 (5.0 Gbps)





Refer to the PCI Express High Performance Reference Design for more information about calculating bandwidth for the hard IP implementation of PCI Express in many Altera FPGAs.