Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 6/03/2020

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Document Table of Contents

8. IP Core Architecture

The Arria V Hard IP for PCI Express implements the complete PCI Express protocol stack as defined in the PCI Express Base Specification. The protocol stack includes the following layers:

  • Transaction Layer—The Transaction Layer contains the Configuration Space, which manages communication with the Application Layer, the RX and TX channels, the RX buffer, and flow control credits.
  • Data Link Layer—The Data Link Layer, located between the Physical Layer and the Transaction Layer, manages packet transmission and maintains data integrity at the link level. Specifically, the Data Link Layer performs the following tasks:
    • Manages transmission and reception of Data Link Layer Packets (DLLPs)
    • Generates all transmission cyclical redundancy code (CRC) values and checks all CRCs during reception
    • Manages the retry buffer and retry mechanism according to received ACK/NAK Data Link Layer packets
    • Initializes the flow control mechanism for DLLPs and routes flow control credits to and from the Transaction Layer
  • Physical Layer—The Physical Layer initializes the speed, lane numbering, and lane width of the PCI Express link according to packets received from the link and directives received from higher layers.
Figure 63.  Arria V Hard IP for PCI Express Using the Avalon-ST Interface
Table 68.  Application Layer Clock Frequencies





125 MHz @ 64 bits or

62.5 MHz @ 64 bits

125 MHz @ 64 bits


125 MHz @ 64 bits

125 MHz @ 64 bits


125 MHz @ 64 bits

125 MHz @ 128 bits


125 MHz @ 128 bits


The following interfaces provide access to the Application Layer’s Configuration Space Registers:

  • The LMI interface
  • The Avalon-MM PCIe reconfiguration interface, which can access any read-only Configuration Space Register
  • In Root Port mode, you can also access the Configuration Space Registers with a Configuration TLP using the Avalon-ST interface. A Type 0 Configuration TLP is used to access the Root Port configuration Space Registers, and a Type 1 Configuration TLP is used to access the Configuration Space Registers of downstream components, typically Endpoints on the other side of the link.

The Hard IP includes dedicated clock domain crossing logic (CDC) between the PHYMAC and Data Link Layers.