Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 6/03/2020

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.1. Avalon‑ST RX Interface

Table 23.  64- or 128‑Bit Avalon-ST RX Datapath The RX data signal can be 64 or 128 bits.






Receive data bus. Refer to figures following this table for the mapping of the Transaction Layer’s TLP information to rx_st_data and examples of the timing of this interface. Note that the position of the first payload dword depends on whether the TLP address is qword aligned. The mapping of message TLPs is the same as the mapping of TLPs with 4‑dword headers. When using a 64-bit Avalon-ST bus, the width of rx_st_data is 64. When using a 128-bit Avalon-ST bus, the width of rx_st_data is 128.



Indicates that this is the first cycle of the TLP when rx_st_valid is asserted.



Indicates that this is the last cycle of the TLP when rx_st_valid is asserted.



Indicates the number of empty qwords in rx_st_data. Not used when rx_st_data is 64 bits. Valid only when rx_st_eop is asserted in 128-bit mode.

For 128‑bit data, only bit 0 applies; this bit indicates whether the upper qword contains data.

  • 128-Bit interface:
    • rx_st_empty = 0, rx_st_data[127:0]contains valid data
    • rx_st_empty = 1, rx_st_data[63:0] contains valid data



Indicates that the Application Layer is ready to accept data. The Application Layer deasserts this signal to throttle the data stream.

If rx_st_ready is asserted by the Application Layer on cycle <n> , then <n + > readyLatency > is a ready cycle, during which the Transaction Layer may assert valid and transfer data.

The RX interface supports a readyLatency of 2 cycles.



Clocks rx_st_data into the Application Layer. Deasserts within 2 clocks of rx_st_ready deassertion and reasserts within 2 clocks of rx_st_ready assertion if more data is available to send.



Indicates that there is an uncorrectable error correction coding (ECC) error in the internal RX buffer. Active when ECC is enabled. ECC is automatically enabled by the Quartus II assembler. ECC corrects single‑bit errors and detects double‑bit errors on a per byte basis.

When an uncorrectable ECC error is detected, rx_st_err is asserted for at least 1 cycle while rx_st_valid is asserted.

Intel recommends resetting the Arria V Hard IP for PCI Express when an uncorrectable double‑bit ECC error is detected.